Analog Devices Inc. LT1792IS8#PBF
- Part No.:
- LT1792IS8#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
LT1792IS8#PBF.pdf
- Description:
- IC OPAMP JFET 1 CIRCUIT 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:2,048
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Product details
Overview
LT1792IS8#PBF from Analog Devices (formerly Linear Technology) is a low-noise, precision JFET-input operational amplifier in an 8-lead SOIC package. It delivers 4.2nV/√Hz input voltage noise at 1kHz, 600µV max input offset voltage, and 5.6MHz gain-bandwidth product with ±15V supplies - optimized for hydrophone, piezoelectric accelerometer, and photodiode front-end amplification where high source impedance and ultra-low noise are critical.
For engineers reviewing the LT1792IS8#PBF datasheet, LT1792IS8#PBF pinout, LT1792IS8#PBF application, or LT1792IS8#PBF equivalent, key selection criteria include verified 100% tested voltage noise (≤6nV/√Hz max), guaranteed performance over –40°C to +85°C, unconditional stability with ≥1000pF capacitive loads, and industry-standard SO-8 pin compatibility with OPA124/AD743 sockets.
Technical Context
The LT1792IS8#PBF uses a large-geometry JFET differential pair to achieve ultra-low voltage noise while maintaining picoampere-level bias current (≤800pA warmed up). Its architecture eliminates phase reversal and supports unity-gain stability even with 1000pF load capacitance - enabling direct replacement in legacy transducer amplifier sockets without compensation redesign.
It is fully specified for ±5V to ±20V dual supplies, with guaranteed operation across –40°C to +85°C (Industrial grade), and includes 100% production testing for voltage noise, slew rate (≥2.0V/µs), and gain-bandwidth (≥2.9MHz at temperature).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Voltage Noise Density | 4.2nV/√Hz @ 1kHz - enables lowest total input-referred noise in >50kΩ source impedance applications |
| Input Offset Voltage | ≤1.0mV (max) over –40°C to +85°C - ensures minimal DC error in precision sensor signal chains |
| Gain-Bandwidth Product | 5.6MHz (typ) @ ±15V - supports stable closed-loop bandwidth up to ~500kHz at G=10 |
| Input Bias Current | ≤800pA (warmed up) - preserves signal integrity with high-Z capacitive transducers (e.g., hydrophones) |
| Common-Mode Range | ±13.0V @ ±15V supplies - allows rail-to-rail input operation within 2V of rails |
| Slew Rate | 2.0V/µs (min) over full temp range - supports fast settling in low-noise instrumentation front ends |
| Supply Current | 5.4mA (max) @ –40°C to +85°C - enables predictable thermal design in SO-8 package (θJA = 130°C/W) |
Pinout & Package
LT1792IS8#PBF is housed in an 8-lead plastic SOIC (SO-8, narrow 0.150") package with standard industry pinout and 1.27mm lead pitch. The package meets JEDEC MS-012 specifications and is RoHS-compliant (Pb-free, #PBF suffix).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VOS ADJ) | Offset Null Terminal A | Connects to wiper of 10k–200k potentiometer tied between V– and V+ for precise input offset trimming |
| 2 (–IN A) | Inverting Input | High-impedance JFET input node; input capacitance = 14pF (differential), supports charge-amplifier configurations |
| 3 (+IN A) | Non-Inverting Input | High-impedance JFET input node; common-mode range extends to within 2V of supply rails |
| 4 (V–) | Negative Supply | Accepts –5V to –20V; must be decoupled locally to minimize noise coupling into input stage |
| 5 (NC) | No Connect | Internally unused; must remain unconnected per datasheet - no routing or grounding |
| 6 (V+) | Positive Supply | Accepts +5V to +20V; power supply rejection ratio ≥83dB (±4.5V to ±20V) |
| 7 (OUT) | Output | Capable of driving ≥10kΩ load to ±12.8V swing; stable with ≥1000pF capacitive loads at unity gain |
| 8 (VOS ADJ) | Offset Null Terminal B | Connects to opposite end of same potentiometer used on Pin 1 - forms balanced null network |
Key Features
| Feature | Design Value |
|---|---|
| 100% tested voltage noise | Guaranteed ≤6nV/√Hz max - eliminates screening for noise-critical transducer amplifiers |
| Unconditional unity-gain stability | Stable with ≥1000pF capacitive loads - removes need for external compensation in sensor interface PCBs |
| Extended temperature guarantee | Full specs guaranteed from –40°C to +85°C - qualified for industrial embedded systems without derating |
| Industry-standard SO-8 pinout | Drop-in compatible with OPA124, AD743, AD745, AD645, AD544, and AD820 sockets - reduces redesign risk |
| Low input bias current drift | ≤40µV/°C max offset drift - maintains accuracy in wide-temperature hydrophone or accelerometer deployments |
Applications
| Hydrophone Amplifier | Piezoelectric Accelerometer Front End |
|---|---|
Use Scenario: Amplifying microvolt-level acoustic signals from underwater hydrophones with source impedances >100MΩ and capacitance 100pF–5000pF. IC Role / Device Role / Timing Role: Primary low-noise charge/voltage amplifier in first-stage signal conditioning, configured as DC-servo integrator to suppress low-frequency drift. Use Value: Achieves 128nV/√Hz output noise at 1kHz (G=20), enabling detection of sub-millivolt signals buried in thermal noise - validated in Linear's TA01 reference design. | Use Scenario: Conditioning charge output from high-sensitivity piezoelectric accelerometers (e.g., B&K 4381) in structural health monitoring systems. IC Role / Device Role / Timing Role: Charge amplifier with DC servo loop (R4C2=R5C3>R1(1+R2/R3)C1) to maintain baseline stability under vibration-induced bias shifts. Use Value: Delivers 0.8mV/pC sensitivity (8.0mV/g) with ≤2.7mV DC output error and 6nV/√Hz input noise - meets MIL-STD-810 shock/vibration test requirements. |
| Photodiode Transimpedance Amplifier | Low-Noise Instrumentation Amplifier Front End |
Use Scenario: Converting photocurrent from Hamamatsu S1336-5BK photodiodes (CD ≈ 1–10pF) into calibrated voltage for spectral analysis. IC Role / Device Role / Timing Role: Transimpedance amplifier with R2C2 > C1R1 compensation, operating in inverting configuration with feedback capacitor CF to control bandwidth. Use Value: Enables 100mV/µW response at 200nm and 330mV/µW at 633nm with <3mV output offset - verified in TA05 reference circuit. | Use Scenario: First-stage gain block in two- or three-op-amp instrumentation amplifiers for medical ECG or precision weigh-scale sensors. IC Role / Device Role / Timing Role: High-Z, low-noise buffer/amplifier driving the input of difference amplifier stages; leverages 10¹¹Ω input resistance and 85dB CMRR. Use Value: Reduces total system noise floor by >6dB vs bipolar alternatives in >10kΩ source impedance conditions - confirmed in TA06 10Hz Chebyshev filter application. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar precision JFET op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT1793CS8#PBF | Lower input bias current (10pA vs 800pA), same 6nV/√Hz noise, but reduced GBW (4.5MHz typ) | Better for ultra-high-Z (>1GΩ) photodiode or electret mic preamps where IB dominates error | Select LT1793CS8#PBF when bias current <50pA is mandatory; accept 20% lower bandwidth and higher cost |
| OPA140AIDR | Lower noise (4.6nV/√Hz), rail-to-rail output, but only specified to +125°C; no VOS ADJ pins | Suitable for automotive cabin sensors requiring extended temp, but lacks offset trim capability | Choose OPA140AIDR for RRO and AEC-Q200 compliance; use only if external offset calibration is acceptable |
Compared with LT1793CS8#PBF and OPA140AIDR, the LT1792IS8#PBF uniquely balances ultra-low voltage noise, guaranteed industrial temperature operation, full offset adjustability, and proven 1000pF capacitive load drive - making it optimal for fixed-gain, high-stability transducer interfaces where layout simplicity and long-term calibration stability are prioritized.
Availability
LT1792IS8#PBF is available at Aetrix Electronics and suitable for hydrophone amplification, piezoelectric sensor conditioning, photodiode transimpedance conversion, and precision instrumentation front ends requiring stable component supply across industrial temperature ranges.
Supply support for LT1792IS8#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing ICs, serving industrial, communications, automotive, and healthcare markets.
The LT1792IS8#PBF belongs to Linear's precision JFET op amp family, engineered specifically for ultra-low-noise amplification of high-impedance capacitive transducers - emphasizing voltage noise minimization, thermal stability, and socket compatibility with legacy designs.
FAQ
What is the maximum guaranteed input voltage noise for LT1792IS8#PBF?
The LT1792IS8#PBF is 100% tested for voltage noise, with a maximum guaranteed value of 6nV/√Hz across the industrial temperature range (–40°C to +85°C). This is measured at 1kHz under ±15V supplies and is documented in the Electrical Characteristics table for the "I" grade. Typical performance is 4.2nV/√Hz, and the distribution shows >95% of units fall below 4.6nV/√Hz.
Does LT1792IS8#PBF support operation from ±5V supplies?
Yes, the LT1792IS8#PBF is fully specified and guaranteed for operation from ±5V supplies. Key parameters including input offset voltage (≤1.3mV max), supply current (≤5.35mA), and gain-bandwidth product (≥2.9MHz) are characterized at ±5V. Reduced supply voltage lowers power dissipation and input bias current, trading dynamic range for improved thermal stability - a documented design option in the datasheet.
Can LT1792IS8#PBF drive large capacitive loads without oscillation?
Yes, the LT1792IS8#PBF is unconditionally stable at unity gain with capacitive loads up to 1000pF, as verified in Figure 13 (Capacitive Load Handling). This eliminates the need for external isolation resistors or compensation networks in transducer interface circuits - a key differentiator versus many JFET op amps that require careful layout or added components to maintain stability.
Is LT1792IS8#PBF pin-compatible with OPA124 or AD743?
Yes, the LT1792IS8#PBF uses the industry-standard SO-8 pinout and is explicitly designed for direct socket replacement of OPA124, AD743, AD745, AD645, AD544, and AD820. Offset nulling is compatible: tie the potentiometer wiper to V– (Pin 4), matching the connection scheme shown in Figure 1a of the datasheet.
What is the thermal resistance (θJA) of LT1792IS8#PBF in SO-8 package?
The LT1792IS8#PBF has a junction-to-ambient thermal resistance (θJA) of 130°C/W for the SO-8 package, as specified in the Absolute Maximum Ratings table. This value assumes standard JEDEC 2S2P board conditions and is critical for calculating die temperature rise - e.g., at 5.4mA supply current and ±15V supplies, power dissipation is ~81mW, resulting in ~10.5°C rise above ambient.
LT1792IS8#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 3.4V/µs
- Gain Bandwidth Product:
- 5.6 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 300 pA
- Voltage - Input Offset:
- 200 µV
- Current - Supply:
- 4.2mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 40 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
LT1792IS8#PBF FAQ
1.How can I place an order for LT1792IS8#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1792IS8#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1792IS8#PBF reliable?
The price and inventory of LT1792IS8#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1792IS8#PBF is usually 5 days.
3.What payment methods are accepted for LT1792IS8#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT1792IS8#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT1792IS8#PBF?
LT1792IS8#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1792IS8#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1792IS8#PBF?
For technical support, including LT1792IS8#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1792IS8#PBF requirements.
6.How does Aetrix verify that LT1792IS8#PBF is sourced from the original manufacturer or authorized distributors?
All LT1792IS8#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1792IS8#PBF meets industry standards.
7.What is the process for return or replacement of LT1792IS8#PBF?
All LT1792IS8#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1792IS8#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1792IS8#PBF part is unused and in its original packaging.
Return procedure for LT1792IS8#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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