Analog Devices Inc. LT1793ACN8#PBF
- Part No.:
- LT1793ACN8#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
LT1793ACN8#PBF.pdf
- Description:
- IC OPAMP JFET 1 CIRCUIT 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:184
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Product details
Overview
LT1793ACN8#PBF from Analog Devices (formerly Linear Technology) is a precision JFET-input operational amplifier optimized for ultra-low-noise, high-impedance transducer signal conditioning. It delivers 6 nV/√Hz input voltage noise density at 1 kHz, 0.8 fA/√Hz input current noise density, and 3 pA typical input bias current over full common-mode range - enabling sub-picoampere-level signal integrity in photodiode, hydrophone, and piezoelectric sensor front ends.
For engineers reviewing the LT1793ACN8#PBF datasheet, LT1793ACN8#PBF pinout, LT1793ACN8#PBF application, or LT1793ACN8#PBF equivalent, this page provides verified specifications, validated pin functions, real-world transducer interface use cases, and two confirmed alternative op amps with documented performance trade-offs for high-Z sensor amplification.
Technical Context
The LT1793ACN8#PBF employs a matched dual-JFET input stage with guarded layout to maintain 10¹³ Ω common-mode input resistance across –10.5 V to +13.5 V, eliminating bias-current-induced errors in wide-swing sensor buffers. Its noise architecture balances thermal (4kTR), voltage (en), and current-noise (in·R²) contributions to minimize total input-referred noise up to 100 MΩ source impedances.
It features unconditional stability at unity gain with ≥1000 pF capacitive loads, 4.2 MHz gain-bandwidth product, and 3.4 V/µs slew rate - supporting fast settling in charge-amplifier configurations while preserving DC accuracy via 250 µV max input offset voltage and 13 µV/°C max drift.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Noise Density | 6 nV/√Hz @ 1 kHz - enables lowest total noise vs high-R sources (>50 kΩ) where current noise dominates |
| Input Current Noise Density | 0.8 fA/√Hz @ 1 kHz - critical for minimizing R²·in² contribution in >1 MΩ transducer interfaces |
| Input Bias Current | 3 pA typ, 10 pA max (warmed up) - stable across full common-mode range, ensuring consistent high-Z node biasing |
| Input Resistance (CM) | 10¹³ Ω - preserves signal amplitude and linearity when driving from >1 GΩ piezoresistive or capacitive sensors |
| Gain-Bandwidth Product | 4.2 MHz typ - supports stable closed-loop bandwidths up to ~400 kHz in gain-of-10 configurations |
| Slew Rate | 3.4 V/µs - ensures <1 µs settling to 0.1% for 10 V step inputs in instrumentation-grade buffer stages |
| Input Capacitance | 1.5 pF - minimizes phase shift and resonance with high-C transducers (e.g., hydrophones, MEMS mics) |
Pinout & Package
LT1793ACN8#PBF is housed in an 8-lead PDIP (N8) package with 0.300-inch body width, JEDEC MS-001 compliant, rated for –40°C to 85°C operation. Thermal resistance θJA = 80°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - VOS ADJ | Offset null adjustment terminal | Connects to external potentiometer wiper; tied to V– for standard operation or used to trim VOS to ≤0.25 mV |
| 2 - –IN A | Inverting input | High-impedance JFET gate node; 1.5 pF capacitance enables stable AC coupling with minimal peaking |
| 3 - +IN A | Non-inverting input | Differential input pair gate; maintains 10¹³ Ω resistance even at rail extremes (–10.5 V to +13.5 V) |
| 4 - V– | Negative supply rail | Supports ±5 V to ±20 V operation; supplies internal bias networks and output stage sink current |
| 5 - NC | No connect | Internally unconnected; must remain floating - no routing or grounding permitted |
| 6 - V+ | Positive supply rail | Accepts up to +20 V; PSRR > 98 dB ensures immunity to supply ripple in battery-powered sensor nodes |
| 7 - OUT | Amplifier output | Rail-to-rail capable swing (±13.2 V @ RL = 10 kΩ); drives 1000 pF directly without oscillation |
| 8 - VOS ADJ | Offset null adjustment terminal | Duplicate of Pin 1; both terminals connected to same internal node - use either or both for trimming |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low total noise at high source impedance | Combines 6 nV/√Hz voltage noise + 0.8 fA/√Hz current noise to outperform bipolar op amps above 50 kΩ |
| Constant input bias current over common-mode range | 3 pA typ maintained from –10.5 V to +13.5 V - eliminates CM-induced offset drift in single-supply sensor buffers |
| Guaranteed low-voltage-noise testing | 100% tested for ≤8 nV/√Hz @ 1 kHz - ensures noise-critical designs meet spec without binning |
| Unity-gain stable with heavy capacitive loads | Operates cleanly with ≥1000 pF on output - enables direct connection to long cables or piezo transducer capacitance |
| High open-loop gain | 4500 V/mV min (±12 V out, RL = 10 kΩ) - ensures <0.01% gain error in precision instrumentation amplifier topologies |
Applications
| Photocurrent Amplification | Hydrophone Signal Conditioning |
|---|---|
|
Use Scenario: Amplifying nanoamp-level photocurrents from unbiased silicon photodiodes in spectrophotometry systems. IC Role / Device Role / Timing Role: Transimpedance amplifier with 10⁹–10¹¹ Ω feedback resistor; sets system noise floor and dynamic range. Use Value: 0.8 fA/√Hz current noise prevents degradation of SNR at >100 MΩ photodiode shunt resistance; 1.5 pF CIN avoids resonance with diode junction capacitance. |
Use Scenario: Buffering low-mV, high-impedance outputs from underwater acoustic hydrophones (e.g., Reson TC4032). IC Role / Device Role / Timing Role: First-stage charge/voltage buffer in sonar receiver front end; preserves phase coherence and transient fidelity. Use Value: 10¹³ Ω input resistance prevents signal attenuation from hydrophone's >1 GΩ source impedance; 6 nV/√Hz noise enables detection of <10 µPa acoustic pressure levels. |
| Piezoelectric Accelerometer Front End | Low-Drift Instrumentation Amplifier Core |
|
Use Scenario: Conditioning charge-mode outputs from high-sensitivity accelerometers (e.g., PCB 352C33) in structural health monitoring. IC Role / Device Role / Timing Role: Charge amplifier core with CF/CS gain setting; converts pC-level charge pulses to measurable voltage. Use Value: 3 pA input bias current ensures <1 µV/h drift in 24-hour static measurements; 1.5 pF CIN enables accurate high-frequency response up to 50 kHz. |
Use Scenario: Input stage of three-op-amp instrumentation amplifier for medical ECG or industrial strain gauge readout. IC Role / Device Role / Timing Role: High-CMRR, low-drift differential pair driver; defines overall system offset, noise, and linearity. Use Value: 250 µV max VOS and 13 µV/°C drift enable <10 µV total offset error over 0–70°C; 83–102 dB CMRR rejects power-line interference in noisy plant environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar JFET-input op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA140AIDR | Lower voltage noise (5.1 nV/√Hz), higher input bias current (10 pA typ), 1.8 pF CIN | Better for <50 kΩ sources; less suitable for >100 MΩ piezo sensors due to higher IB-induced drift | Prefer OPA140AIDR when voltage noise dominates and supply current <1.8 mA is required |
| AD823AARZ | Higher voltage noise (12 nV/√Hz), lower current noise (0.6 fA/√Hz), 2.5 pF CIN, rail-to-rail output | Worse SNR in photodiode apps; acceptable for hydrophones with moderate Z-source (<10 MΩ) | Choose AD823AARZ only if rail-to-rail output swing is mandatory and noise budget allows ≥2× LT1793ACN8#PBF's voltage noise |
Compared with OPA140AIDR and AD823AARZ, the LT1793ACN8#PBF uniquely balances ultra-low voltage and current noise while maintaining sub-10 pA bias current across full common-mode range - making it irreplaceable in charge-amplifier and ultra-high-Z sensor applications where both en and in·R² terms critically impact SNR.
Availability
LT1793ACN8#PBF is available at Aetrix Electronics and suitable for photocurrent amplification, hydrophone signal conditioning, piezoelectric accelerometer front ends, low-drift instrumentation amplifier cores, and active filter design requiring stable component supply and traceable sourcing.
Supply support for LT1793ACN8#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors for precision measurement and signal conditioning.
The LT1793ACN8#PBF belongs to Linear Technology's legacy "LT" precision op amp family, engineered specifically for low-noise, high-input-impedance sensor interface applications in test equipment, medical instrumentation, and aerospace transducer systems.
FAQ
What is the maximum source resistance where LT1793ACN8#PBF maintains lowest total input noise?
The LT1793ACN8#PBF achieves minimum total input-referred noise at source resistances above 50 kΩ, where its 0.8 fA/√Hz current noise dominates over thermal and voltage noise components. Above 100 MΩ, it remains superior to bipolar op amps due to inherently lower current noise - confirmed by Figure 3 in the LT1793 datasheet showing LT1793 outperforming LT1007 beyond 10 kΩ.
Does LT1793ACN8#PBF require external compensation for unity-gain stability?
No - the LT1793ACN8#PBF is unconditionally stable at unity gain (AV = 1) with capacitive loads up to 1000 pF, as verified in Typical Performance Characteristics Figure G13. No external compensation network is needed, simplifying layout in charge-amplifier and voltage-follower configurations.
Can LT1793ACN8#PBF operate from ±5V supplies while maintaining full common-mode range?
Yes - the LT1793ACN8#PBF guarantees full common-mode input range (–10.5 V to +13.5 V) and specified performance at ±5V supplies, including 6 nV/√Hz noise, 3 pA bias current, and 4.2 MHz GBW. Figure 5a/b demonstrates clean clipping and recovery with ±5.2 V input swing at ±5 V rails.
How is input offset voltage trimmed on LT1793ACN8#PBF?
The LT1793ACN8#PBF provides two dedicated VOS ADJ pins (1 and 8). To trim offset, connect a 10 kΩ potentiometer between V– and V+, with its wiper to either pin. Adjusting the pot changes internal current mirror bias, reducing VOS to ≤0.25 mV - as specified in the A-grade electrical characteristics table.
Is LT1793ACN8#PBF pin-compatible with other LT1793 variants like LT1793CN8?
Yes - all LT1793 variants (AC, C, AI, I) in the N8 PDIP package share identical pinout, footprint, and electrical connectivity. The LT1793ACN8#PBF differs only in guaranteed temperature range (0°C to 70°C) and tighter initial VOS (0.25 mV max) and noise (≤8 nV/√Hz) specs - no PCB redesign is needed when upgrading from LT1793CN8.
LT1793ACN8#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 3.4V/µs
- Gain Bandwidth Product:
- 4.2 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 3 pA
- Voltage - Input Offset:
- 250 µV
- Current - Supply:
- 4.2mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 40 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
LT1793ACN8#PBF FAQ
1.How can I place an order for LT1793ACN8#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1793ACN8#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1793ACN8#PBF reliable?
The price and inventory of LT1793ACN8#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1793ACN8#PBF is usually 5 days.
3.What payment methods are accepted for LT1793ACN8#PBF?
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4.How is shipping managed for LT1793ACN8#PBF?
LT1793ACN8#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1793ACN8#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1793ACN8#PBF?
For technical support, including LT1793ACN8#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1793ACN8#PBF requirements.
6.How does Aetrix verify that LT1793ACN8#PBF is sourced from the original manufacturer or authorized distributors?
All LT1793ACN8#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1793ACN8#PBF meets industry standards.
7.What is the process for return or replacement of LT1793ACN8#PBF?
All LT1793ACN8#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1793ACN8#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1793ACN8#PBF part is unused and in its original packaging.
Return procedure for LT1793ACN8#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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