Analog Devices Inc. LT1793AIN8#PBF
- Part No.:
- LT1793AIN8#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
LT1793AIN8#PBF.pdf
- Description:
- IC OPAMP JFET 1 CIRCUIT 8DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT1793AIN8#PBF from Analog Devices (formerly Linear Technology) is a precision JFET-input operational amplifier optimized for ultra-low-noise, high-impedance signal conditioning. It delivers 6 nV/√Hz input voltage noise density at 1 kHz, 0.8 fA/√Hz input current noise density, and 3 pA typical input bias current over full common-mode range - enabling accurate amplification of signals from photodiodes, hydrophones, and piezoelectric accelerometers. Its 4.2 MHz gain-bandwidth product and unconditional stability with ≥1000 pF capacitive loads support robust sensor front-end designs.
For engineers reviewing the LT1793AIN8#PBF datasheet, LT1793AIN8#PBF pinout, LT1793AIN8#PBF application, or LT1793AIN8#PBF equivalent, key selection criteria include verified low-frequency 1/f noise performance (2.4 µVP-P, 0.1–10 Hz), guaranteed 1013 Ω common-mode input resistance, 1.5 pF input capacitance, ±13.2 V output swing into 10 kΩ, and 100% tested voltage noise and slew rate (3.4 V/µs) at ±15 V supply.
Technical Context
The LT1793AIN8#PBF employs a JFET differential input stage with matched gate structures to maintain sub-10 pA bias current across –10.5 V to +13.5 V common-mode voltage range, eliminating input-stage phase reversal and ensuring stable DC-coupled transducer interfacing. Its noise architecture balances thermal and current noise contributions, achieving minimum total input-referred noise at source impedances >50 kΩ via ultra-low 0.8 fA/√Hz current noise.
Internally compensated for unity-gain stability, it features a 4.2 MHz gain-bandwidth product with 3.4 V/µs slew rate and >100 dB PSRR/CMRR at DC, supporting precision instrumentation amplifier front ends, active filters, and charge amplifiers without external compensation or guard traces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Noise Density | 6 nV/√Hz @ 1 kHz - enables lowest total noise in high-Z transducer interfaces above 50 kΩ source resistance |
| Input Current Noise Density | 0.8 fA/√Hz @ 1 kHz - minimizes current-noise-induced error in photodiode and piezoelectric applications |
| Input Bias Current | 3 pA typ, 10 pA max (warmed up) - ensures <1 µV error from 1 GΩ source impedance at 25°C |
| Input Resistance | 1013 Ω common-mode - preserves signal integrity in electrochemical and MEMS sensor buffers |
| Gain-Bandwidth Product | 4.2 MHz typ - supports stable closed-loop gains up to 100× at 42 kHz with 1000 pF load |
| Slew Rate | 3.4 V/µs min - handles fast transient signals in accelerometer and hydrophone pulse detection |
| Input Capacitance | 1.5 pF - maintains >60 dB gain flatness to 1 MHz in noninverting configurations |
| Output Swing | ±13.2 V @ RL = 10 kΩ - delivers full dynamic range into standard ±15 V supply rails |
Pinout & Package
LT1793AIN8#PBF is housed in an 8-lead PDIP (N8) package with 0.300-inch body width, JEDEC MS-001 compliant, rated for –40°C to +85°C operation. Thermal resistance θJA = 80°C/W enables reliable operation at ≤5.2 mA quiescent current without heatsinking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - VOS ADJ | Offset null terminal | Connects to potentiometer wiper for manual offset trimming; tied to V– for default operation |
| 2 - –IN A | Inverting input | Differential node for feedback networks; 1.5 pF capacitance requires guard ring in high-Z layouts |
| 3 - +IN A | Non-inverting input | High-impedance node (1013 Ω); must be guarded to prevent leakage-induced drift |
| 4 - V– | Negative supply | Reference for internal biasing; accepts –20 V absolute max; connects to ground in single-supply configs |
| 5 - NC | No connect | Internal die pad not bonded; leave unconnected per datasheet to avoid parasitic coupling |
| 6 - V+ | Positive supply | Reference for internal biasing; accepts +20 V absolute max; decouple with ≥0.1 µF ceramic |
| 7 - OUT | Amplifier output | Capable of driving ≥1000 pF directly; slew-limited to 3.4 V/µs under 2 kΩ load |
| 8 - VOS ADJ | Offset null terminal | Duplicate of Pin 1; both terminals used jointly for 2-terminal nulling configuration |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low total input noise | 6 nV/√Hz voltage + 0.8 fA/√Hz current noise enables best-in-class SNR for ZS > 50 kΩ |
| Stable high-Z input stage | 1013 Ω input resistance maintained across full common-mode range prevents bias-current drift |
| Guaranteed noise performance | 100% tested voltage noise and slew rate ensures production consistency for metrology-grade designs |
| Capacitive-load immunity | Unconditionally stable with ≥1000 pF load eliminates need for isolation resistors in photodiode buffers |
| Extended temperature validation | A-grade parts 100% temperature-tested from –40°C to +85°C for industrial sensor reliability |
Applications
| Photocurrent Amplification | Hydrophone Signal Conditioning |
|---|---|
Use Scenario: Amplifying weak photocurrents from silicon PIN photodiodes in spectrophotometry systems operating at 633 nm wavelength. IC Role / Device Role / Timing Role: Transimpedance amplifier with 330 mV/µW responsivity scaling and DC servo stabilization. Use Value: 1.5 pF input capacitance and 0.8 fA/√Hz current noise minimize integration-time-dependent noise floor, enabling sub-picoampere detection. | Use Scenario: Low-noise preamplification of underwater acoustic signals from piezoelectric hydrophones in oceanographic monitoring. IC Role / Device Role / Timing Role: High-input-impedance voltage buffer with 1013 Ω RIN preserving signal fidelity from 100 MΩ+ transducer sources. Use Value: 6 nV/√Hz voltage noise dominates only below 5 kΩ source resistance - optimal for hydrophone's moderate-Z output. |
| Piezoelectric Accelerometer Front End | Low-Noise Instrumentation Amplifier Core |
Use Scenario: Charge-mode amplification of vibration signals from B&K 4381 accelerometers in structural health monitoring. IC Role / Device Role / Timing Role: Inverting charge amplifier with CF/CS gain setting and RB balancing network for thermal-current noise cancellation. Use Value: Verified 8 nV/√Hz output noise at 1 kHz and 0.25 mV max VOS ensure <0.1% amplitude error in g-force measurements. | Use Scenario: First-stage gain block in three-op-amp instrumentation amplifiers for medical ECG/EEG acquisition. IC Role / Device Role / Timing Role: Precision input amplifier providing 100 dB CMRR and 85 dB PSRR to reject common-mode interference. Use Value: 250 µV max VOS and 5 µV/°C drift enable <1 µV baseline stability over clinical temperature ranges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar JFET-input op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA140AIDR | Lower voltage noise (5.1 nV/√Hz), higher supply current (1.8 mA), no VOS ADJ pins | Lacks offset trim capability; unsuitable for DC-coupled systems requiring <10 µV drift | Select when lowest voltage noise dominates and offset adjustment is unnecessary |
| AD823ARZ | Higher input bias current (1 pA max), lower GBW (16 MHz), bipolar input stage | Current noise 10× higher (8 fA/√Hz); degrades SNR above 5 kΩ source resistance | Select only for low-Z (<1 kΩ) sensor interfaces where bandwidth outweighs noise |
Compared with OPA140AIDR and AD823ARZ, LT1793AIN8#PBF uniquely combines 100% tested noise/slew performance, dual VOS ADJ pins for precision trimming, and guaranteed 1013 Ω input resistance across –40°C to +85°C - making it irreplaceable in metrology-grade high-Z transducer front ends.
Availability
LT1793AIN8#PBF is available at Aetrix Electronics and suitable for photocurrent amplification, hydrophone signal conditioning, piezoelectric accelerometer front ends, low-noise instrumentation amplifier cores, and active filter designs requiring stable component supply across industrial, test & measurement, and aerospace programs.
Supply support for LT1793AIN8#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors for precision instrumentation and signal chain applications.
The LT1793 series was designed specifically for ultra-low-noise, high-input-impedance sensor signal conditioning - targeting photodiode, hydrophone, and piezoelectric transducer interfaces where voltage and current noise must be simultaneously minimized.
FAQ
What is the maximum guaranteed input bias current for LT1793AIN8#PBF over temperature?
The LT1793AIN8#PBF has a maximum guaranteed input bias current of 20 pA over the full –40°C to +85°C operating range, with 10 pA max specified at 25°C after warm-up. This value is validated per the IB parameter in the "LT1793AC/LT1793AI" electrical characteristics table, confirming its suitability for high-impedance transducer applications where leakage-induced errors must remain below 1 µV across environmental extremes. The LT1793AIN8#PBF achieves this via JFET input matching and on-die thermal compensation.
Does LT1793AIN8#PBF require external compensation for unity-gain stability?
No, LT1793AIN8#PBF is internally compensated and unconditionally stable at unity gain, even with 1000 pF capacitive loads. This is confirmed by the "unconditionally stable for gains of 1 or more" statement in the product description and validated in Figure 13 (Capacitive Load Handling) of the datasheet, which shows <5% overshoot at AV = 1 with CL = 1000 pF. The LT1793AIN8#PBF's compensation network eliminates need for external isolation resistors in photodiode TIA designs - a key differentiator versus older JFET op amps like OPA111.
How is offset voltage adjusted on LT1793AIN8#PBF?
LT1793AIN8#PBF provides two dedicated offset null terminals (Pins 1 and 8) that accept a 10 kΩ potentiometer wired between V– and V+, with the wiper connected to either pin. Per Figure 2a in the datasheet, this configuration allows ±13 mV adjustment range. For finer control, Figure 2b shows adding series resistors to limit range to ±1.3 mV. The LT1793AIN8#PBF's dual-null architecture enables precise DC calibration in instrumentation amplifier front ends without affecting common-mode rejection.
What is the input voltage range specification for LT1793AIN8#PBF at ±15 V supply?
At ±15 V supply, LT1793AIN8#PBF guarantees an input voltage range of –10.5 V to +13.5 V (referred to V– and V+, respectively), as specified in the "ELECTRICAL CHARACTERISTICS" table under VCM. This rail-to-rail common-mode capability - combined with absence of phase reversal - allows direct interfacing with sensors whose output exceeds traditional op amp limits, such as piezoelectric accelerometers generating ±12 V signals. The LT1793AIN8#PBF maintains 250 µV VOS and 1013 Ω RIN across this full range.
Is LT1793AIN8#PBF qualified for extended temperature operation?
Yes, LT1793AIN8#PBF is the Industrial-grade variant, guaranteed to meet all specifications from –40°C to +85°C. Unlike commercial-grade LT1793CN8, the "I" suffix denotes full temperature-range testing and qualification, including 100% screening of voltage noise, slew rate, and gain-bandwidth product across the entire range. This makes LT1793AIN8#PBF suitable for deployment in outdoor instrumentation, avionics sensor nodes, and industrial PLC analog input modules where ambient temperatures exceed 70°C.
LT1793AIN8#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 3.4V/µs
- Gain Bandwidth Product:
- 4.2 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 3 pA
- Voltage - Input Offset:
- 250 µV
- Current - Supply:
- 4.2mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 40 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
LT1793AIN8#PBF FAQ
1.How can I place an order for LT1793AIN8#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1793AIN8#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1793AIN8#PBF reliable?
The price and inventory of LT1793AIN8#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1793AIN8#PBF is usually 5 days.
3.What payment methods are accepted for LT1793AIN8#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT1793AIN8#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT1793AIN8#PBF?
LT1793AIN8#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1793AIN8#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1793AIN8#PBF?
For technical support, including LT1793AIN8#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1793AIN8#PBF requirements.
6.How does Aetrix verify that LT1793AIN8#PBF is sourced from the original manufacturer or authorized distributors?
All LT1793AIN8#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1793AIN8#PBF meets industry standards.
7.What is the process for return or replacement of LT1793AIN8#PBF?
All LT1793AIN8#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1793AIN8#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1793AIN8#PBF part is unused and in its original packaging.
Return procedure for LT1793AIN8#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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