Analog Devices Inc. LT1952EGN#PBF
- Part No.:
- LT1952EGN#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
LT1952EGN#PBF.pdf
- Description:
- IC REG CTRLR FWRD CONV 16SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:100
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LT1952EGN#PBF from Analog Devices (formerly Linear Technology) is a current-mode PWM controller optimized for single-switch synchronous forward converters. It delivers synchronous rectifier control, programmable volt-second clamp (1.32V SD_VSEC threshold), 107mV precision overcurrent detection, and 100kHz–500kHz programmable switching frequency. It enables high-efficiency 25W–500W telecom bus converters with >50% duty cycle operation.
For engineers reviewing the LT1952EGN#PBF datasheet, LT1952EGN#PBF pinout, LT1952EGN#PBF application, or LT1952EGN#PBF equivalent, key selection considerations include its adaptive maximum duty cycle clamp, low 460µA startup current, true op-amp error amplifier, programmable slope compensation, and 16-pin SSOP package with dedicated SOUT/OUT timing control for synchronous rectification.
Technical Context
The LT1952EGN#PBF implements current-mode control with a true op-amp error amplifier (65–85dB open-loop gain, 3MHz unity-gain bandwidth) and independent 107mV OC threshold unaffected by duty cycle. Its volt-second clamp uses resistor-ratio programming via SD_VSEC (1.32V turn-on threshold) and SS_MAXDC to dynamically limit duty cycle based on input voltage-enabling reliable >50% operation without transformer saturation.
It features dual gate drivers: OUT provides ±1A peak drive clamped to 13V for the primary MOSFET; SOUT delivers ±50mA clamped to 12V with programmable delay (via DELAY pin) to synchronize secondary-side synchronous rectifiers. Leading edge blanking (adjustable via BLANK pin) and soft-start latching (triggered by VIN < 8.75V, SD_VSEC < 1.32V, or OC > 107mV) ensure robust fault recovery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | Current-mode synchronous forward controller with single-primary-MOSFET support |
| Switching Frequency | 100kHz–500kHz programmable via ROSC resistor; synchronizable up to 1.5×fOSC |
| Overcurrent Threshold | Precision 107mV at OC pin-enables hiccup-mode short-circuit protection independent of duty cycle |
| Volt-Second Clamp | SD_VSEC pin with 1.32V threshold and 10µA hysteresis-allows resistor-based UVLO and adaptive duty cycle limiting |
| Startup Current | 460µA typical at VIN = 14.0V-enables micropower bootstrap start-up from high-input-voltage rails |
| Output Drivers | OUT: ±1A gate drive, 13V clamp; SOUT: ±50mA sync signal, 12V clamp, adjustable delay relative to OUT |
| Error Amplifier | True op-amp with 1.226V FB reference, 65–85dB gain, 3MHz bandwidth-supports wide-range compensation networks |
Pinout & Package
LT1952EGN#PBF is housed in a 16-pin plastic SSOP (GN) package with exposed pad thermal enhancement. Pin pitch is 0.65mm; body dimensions are 5.0mm × 6.2mm × 1.75mm (max height).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| COMP (1) | Error amplifier output | Drives external compensation network; 0.8V–2.5V range maps to 0–220mV ISENSE; disabled when FB = VREF |
| FB (2) | Feedback input | Compares output voltage (via resistor divider) against 1.226V internal reference; disables COMP when tied to VREF |
| ROSC (3) | Oscillator programming | Resistor-to-ground sets fOSC from 100kHz–500kHz; nominal pin voltage = 1.0V |
| SYNC (4) | External clock input | Logic-compatible sync input (10%–90% duty); unused pin may be left open or grounded |
| SS_MAXDC (5) | Soft-start & max duty control | Capacitor/resistor network sets soft-start ramp; voltage sets adaptive duty clamp (e.g., 1.84V + 1.32V SD_VSEC = 72% clamp) |
| VREF (6) | 2.5V reference output | Supplies internal circuitry and external bias; capable of sourcing 2.5mA; requires 0.1µF ceramic bypass |
| SD_VSEC (7) | UVLO & volt-second clamp | 1.32V threshold with 10µA hysteresis-defines system UVLO and dynamically scales max duty cycle vs input voltage |
| GND (8) | Analog ground | Reference for FB, COMP, and internal analog blocks; separate from PGND |
| BLANK (9) | Leading edge blanking control | Resistor-to-ground programs blanking duration (180–540ns) to suppress switching noise false trips |
| ISENSE (10) | Primary current sense input | Connects to MOSFET source resistor; slope compensation programmed via series resistor |
| OC (11) | Overcurrent comparator input | Direct connection to sense resistor; triggers soft-start latch at precise 107mV threshold |
| DELAY (12) | SOUT-to-OUT timing offset | Resistor-to-ground programs delay (40–120ns) for optimal synchronous rectifier timing |
| PGND (13) | Power ground | Return path for OUT/SOUT drivers and high-current paths; separate from analog GND |
| OUT (14) | Primary MOSFET gate driver | ±1A peak drive, 13V clamp, active pull-off in shutdown; drives N-channel FET |
| VIN (15) | Main supply input | Operates from 25V max; 14.25V ON / 8.75V OFF thresholds; 460µA startup current |
| SOUT (16) | Synchronous rectifier sync output | ±50mA peak, 12V clamp, phase-aligned with OUT; used to drive secondary-side FETs |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous rectifier control | Dual outputs (SOUT/OUT) with programmable timing delay enable high-efficiency secondary-side synchronous rectification in forward topology |
| Adaptive volt-second clamp | Resistor-ratio-based SD_VSEC/SS_MAXDC interface eliminates capacitor drift dependency and enables >50% duty cycle without transformer saturation |
| Low-stress hiccup protection | 107mV OC threshold + soft-start latch + immediate SOUT/OUT shutdown prevent thermal runaway during overloads |
| True op-amp error amplifier | 65–85dB gain and 3MHz bandwidth allow stable compensation across wide load/transient conditions without loop stability compromises |
| Programmable slope compensation | Resistor-series to ISENSE pin adjusts ramp slope to match inductor DCR and MOSFET characteristics-optimizing loop bandwidth |
Applications
| Telecom Bus Converter | Industrial DC/DC Supply |
|---|---|
Use Scenario: 36V–72V input telecom power system delivering regulated 12V/20A semi-regulated bus power using forward topology. IC Role / Device Role / Timing Role: Primary-side PWM controller managing single MOSFET switch, synchronous rectifier timing (SOUT→OUT delay), and adaptive duty cycle clamp for transformer reset. Use Value: Enables >50% duty cycle operation at high input voltage, reducing MOSFET stress and improving transformer utilization versus fixed 50% clamp solutions. | Use Scenario: Isolated 48V input industrial power supply delivering 5V/10A to PLC I/O modules with strict efficiency and reliability requirements. IC Role / Device Role / Timing Role: Forward converter controller providing isolated feedback via optocoupler to COMP, programmable UVLO (SD_VSEC), and hiccup-mode overload protection. Use Value: Precision 107mV OC threshold ensures consistent short-circuit response across temperature; low 460µA startup current supports auxiliary winding-free start-up. |
| Distributed Power Architecture | High-Efficiency Server PSU |
Use Scenario: 24V–48V intermediate bus powering multiple point-of-load converters in data center rack systems. IC Role / Device Role / Timing Role: Semi-regulated bus converter controller with programmable frequency synchronization (SYNC pin) to reduce EMI in multi-converter systems. Use Value: SYNC capability allows interleaving with other converters up to 1.5×fOSC, minimizing input/output ripple and easing EMI filter design. | Use Scenario: High-density 12V output server power supply requiring >94% efficiency and compact 16-pin SSOP footprint. IC Role / Device Role / Timing Role: Primary-side controller driving SiC MOSFET with fast OUT driver (50ns rise/30ns fall) and programmable leading edge blanking (BLANK pin). Use Value: 13V OUT clamp and ±1A drive support wide VGS range FETs; adjustable blanking prevents false trips with fast-switching SiC devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar forward converter controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT3748EMSE#PBF | Integrated transformer-isolation feedback; no external optocoupler needed; higher 75V VIN max; no SOUT pin | Designed for isolated flyback, not forward; lacks synchronous rectifier timing control | Select LT3748EMSE#PBF only for flyback designs requiring primary-side regulation without optocoupler |
| UCC2891DR | Fixed 500kHz frequency; no programmable volt-second clamp; no SOUT output; 16-pin SOIC (not SSOP) | Targeted at cost-sensitive forward converters where adaptive duty cycle clamp is unnecessary | Choose UCC2891DR when board space allows SOIC and system input voltage is stable enough to avoid transformer saturation risk |
Compared with LT3748EMSE#PBF and UCC2891DR, the LT1952EGN#PBF uniquely combines adaptive volt-second clamping, dual synchronized outputs (SOUT/OUT), and true op-amp compensation-making it the only option among the three qualified for high-reliability, variable-input forward converters demanding >50% duty cycle and synchronous rectification.
Availability
LT1952EGN#PBF is available at Aetrix Electronics and suitable for telecommunications power supplies, industrial distributed power systems, and isolated DC/DC converters requiring stable component supply, extended temperature operation (–40°C to 125°C), and long-term lifecycle continuity.
Supply support for LT1952EGN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for all Linear ICs including the LT1952 series.
The LT1952EGN#PBF belongs to Linear's high-efficiency PWM controller product line, designed specifically for single-switch forward converter topologies where transformer reset margin, synchronous rectification timing, and micropower startup are critical system requirements.
FAQ
What is the maximum duty cycle supported by the LT1952EGN#PBF under varying input voltage conditions?
The LT1952EGN#PBF does not fix maximum duty cycle; instead, it implements an adaptive volt-second clamp via SD_VSEC and SS_MAXDC pins. With SD_VSEC = 1.32V and SS_MAXDC = 1.84V, the clamp is 72% at fOSC = 200kHz. As input voltage rises, SD_VSEC voltage increases (via resistor divider), causing the clamp to decrease-preventing transformer saturation. This dynamic behavior is confirmed in Figure 22 of the datasheet.
How does the LT1952EGN#PBF achieve hiccup-mode short-circuit protection?
The LT1952EGN#PBF triggers hiccup-mode protection when the OC pin exceeds its precision 107mV threshold. This immediately latches a soft-start event, halting both SOUT and OUT switching. The SS_MAXDC pin is discharged and remains held below 0.45V until all faults clear (VIN > 14.25V, SD_VSEC > 1.32V, OC < 107mV), after which soft-start resumes. This behavior is explicitly detailed in the Timing Diagram (Figure 1) and Operation section.
Can the LT1952EGN#PBF be used with SiC or GaN MOSFETs, and what design adjustments are required?
Yes-the LT1952EGN#PBF supports wide-bandgap FETs. Key adjustments include: (1) increasing RBLANK to extend leading edge blanking (e.g., 120kΩ for 540ns) to suppress fast-switching noise; (2) selecting RSLOPE to match the FET's dV/dt-induced current sense error; and (3) verifying OUT/SOUT rise/fall times (50ns/30ns) meet gate drive requirements. These are validated in Figures G15–G16 and the "Slope Compensation" subsection.
What is the purpose of the SOUT pin on the LT1952EGN#PBF, and how is its timing controlled?
The SOUT pin on the LT1952EGN#PBF provides a synchronized gate drive signal for secondary-side synchronous rectifiers in forward converters. Its rising edge is intentionally delayed relative to OUT by tDELAY (programmed via DELAY pin resistor). Typical delay ranges from 40ns to 120ns, allowing precise timing alignment to minimize body diode conduction loss in SR FETs-confirmed in Figure 2 and Electrical Characteristics Table (tDELAY parameter).
Does the LT1952EGN#PBF require an external optocoupler for isolated feedback, and how is the COMP pin used in that configuration?
Yes-when used in isolated forward converters, the LT1952EGN#PBF requires an optocoupler between the secondary-side error amplifier and the COMP pin. In this configuration, the COMP pin acts as the optocoupler's collector node. To reduce quiescent current, FB is tied to VREF to disable the internal error amplifier, lowering COMP pin current to (COMP – 0.7)/40k µA-explicitly stated in the PIN FUNCTIONS section for Pin 1 (COMP).
LT1952EGN#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Positive, Isolation Capable
- Topology:
- Forward Converter
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 9.25V ~ 25V
- Frequency - Switching:
- 100kHz ~ 500kHz
- Duty Cycle (Max):
- 90%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Enable, Frequency Control
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
LT1952EGN#PBF FAQ
1.How can I place an order for LT1952EGN#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1952EGN#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1952EGN#PBF reliable?
The price and inventory of LT1952EGN#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1952EGN#PBF is usually 5 days.
3.What payment methods are accepted for LT1952EGN#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT1952EGN#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT1952EGN#PBF?
LT1952EGN#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1952EGN#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1952EGN#PBF?
For technical support, including LT1952EGN#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1952EGN#PBF requirements.
6.How does Aetrix verify that LT1952EGN#PBF is sourced from the original manufacturer or authorized distributors?
All LT1952EGN#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1952EGN#PBF meets industry standards.
7.What is the process for return or replacement of LT1952EGN#PBF?
All LT1952EGN#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1952EGN#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1952EGN#PBF part is unused and in its original packaging.
Return procedure for LT1952EGN#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LT1952EGN#PBF Tags

-
UCC28C45DR
Texas Instruments

-
UCC28C40DR
Texas Instruments

-
UCC28C43DR
Texas Instruments

-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments

-
MIC2102YML-TR
Microchip Technology

-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments

-
LM5155DSSR
Texas Instruments

-
LM25085MYX/NOPB
Texas Instruments

-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

