Analog Devices Inc. LT3030IFE#TRPBF
- Part No.:
- LT3030IFE#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LT3030IFE#TRPBF.pdf
- Description:
- IC REG LINEAR POS ADJ 20TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT3030IFE#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel, micropower, low-noise, low-dropout linear regulator with independent 750mA and 250mA outputs, 300mV typical dropout voltage at full load, 20μVRMS output noise (10Hz–100kHz), and 120μA/75μA quiescent current - designed for battery-powered microprocessor core/logic supplies and post-regulation of switching converters.
For engineers reviewing the LT3030IFE#TRPBF datasheet, LT3030IFE#TRPBF pinout, LT3030IFE#TRPBF application, or LT3030IFE#TRPBF equivalent, this page delivers verified specifications, thermal-enhanced 20-lead TSSOP package details, dual-channel shutdown control with <1μA per-channel shutdown current, PWRGD flags, reverse-battery protection, and stable operation with ≥10μF/3.3μF ceramic output capacitors.
Technical Context
The LT3030IFE#TRPBF integrates two independent LDO regulators sharing common ground and thermal coupling but operating with separate input supplies (1.7V–20V), adjustable outputs (1.220V reference), and precision shutdown thresholds (1.09V to 1.33V). Each channel features foldback current limiting, thermal shutdown with hysteresis, and reverse-current protection.
Its architecture supports dual-rail sequencing via independent SHDN1/SHDN2 logic inputs, PWRGD1/PWRGD2 open-collector status flags indicating >90% nominal output regulation, and BYP1/BYP2 pins enabling 20μVRMS noise reduction with 10nF capacitors - all while maintaining stability with low-ESR ceramic, tantalum, or aluminum electrolytic output capacitors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 750mA (OUT1), 250mA (OUT2) - supports high-current core rails and low-current auxiliary supplies simultaneously |
| Dropout Voltage | 300mV typical at 750mA/250mA - enables regulation from low-input sources like single-cell Li-ion or buck converter outputs |
| Output Noise | 20μVRMS (10Hz–100kHz with 10nF BYP cap) - meets stringent noise requirements for RF, ADC, and PLL power domains |
| Quiescent Current | 120μA (OUT1), 75μA (OUT2) - extends battery life in always-on portable systems |
| Shutdown Current | <1μA per channel - enables ultra-low-power deep-sleep modes without external isolation |
| Reference Voltage | 1.220V ±12mV - sets precise adjustable output range (1.220V–19.5V) with minimal ADJ pin bias error (30nA) |
| Input Voltage Range | 1.7V to 20V - accommodates wide-range DC sources including automotive, industrial, and multi-cell battery inputs |
Pinout & Package
The LT3030IFE#TRPBF is packaged in a thermally enhanced 20-lead plastic TSSOP (FE package) with exposed pad (Pin 21) electrically and thermally connected to GND. Soldering the exposed pad to PCB ground is mandatory for specified θJA = 28°C/W and reliable thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OUT1 (Pins 1,2) | Main high-current output | Delivers up to 750mA; requires ≥10μF ceramic output capacitor for stability |
| OUT2 (Pins 7,8) | Secondary low-current output | Delivers up to 250mA; requires ≥3.3μF ceramic output capacitor |
| GND (Pins 3,4,5,6,11,12,13,15,16,19,20, Exposed Pad 21) | Common ground reference | All GND pins and exposed pad must be tied to system ground plane; critical for thermal dissipation and load regulation |
| IN1 (Pins 17,18), IN2 (Pins 13,14) | Independent input supplies | Each channel accepts separate 1.7V–20V inputs; reverse-battery protected |
| SHDN1 (Pin 20), SHDN2 (Pin 11) | Independent shutdown control | Logic-low activates shutdown (<1μA IQ); precision threshold (1.09V–1.33V) enables UVLO functionality |
| PWRGD1 (Pin 19), PWRGD2 (Pin 12) | Power-good status flag | Open-collector output asserting when VOUT ≥90% nominal; requires external pull-up resistor |
| ADJ1 (Pin 1), ADJ2 (Pin 10) | Feedback reference input | 1.220V reference node; regulates output via external resistor divider; 30nA bias current minimizes divider error |
| BYP1 (Pin 2), BYP2 (Pin 9) | Noise-reduction bypass terminal | Connects 10nF capacitor to corresponding OUT pin to reduce output noise to 20μVRMS and improve transient response |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent LDO channels | Enables simultaneous regulation of asymmetric rails (e.g., 1.8V/750mA + 1.5V/250mA) without cross-talk or shared failure modes |
| Reverse-battery & reverse-current protection | Prevents damage and load discharge during incorrect battery insertion or input disconnection - no external diodes required |
| Channel-to-channel isolation | ≥60dB ripple rejection between channels ensures clean power delivery in mixed-signal systems with sensitive analog/RF sections |
| Thermal shutdown with hysteresis | Protects against sustained overload; automatic recovery after cooldown prevents latch-up in intermittent thermal stress conditions |
| Stable with low-ESR capacitors | Operates reliably with 10μF/3.3μF ceramic output caps - eliminates need for bulky, aging-prone electrolytics in space-constrained designs |
Applications
| Microprocessor Core Supply | Post-Regulator for Switching Supplies |
|---|---|
Use Scenario: Powering ARM Cortex-A series CPU cores requiring tightly regulated, low-noise 1.2V–1.8V at up to 750mA during burst-mode operation. IC Role / Device Role / Timing Role: Primary LDO delivering clean, sequenced core voltage with fast transient response and PWRGD confirmation for boot validation. Use Value: 20μVRMS noise and 300mV dropout enable stable core operation directly from 2.5V buck converter outputs, reducing system BOM count. | Use Scenario: Cleaning residual ripple from a 5V buck converter feeding an analog front-end (AFE) requiring ultra-low-noise 3.3V supply. IC Role / Device Role / Timing Role: Secondary LDO channel (OUT2) acting as low-noise post-regulator with independent BYP2 filtering. Use Value: 60dB channel isolation and 20μVRMS noise ensure AFE SNR remains unaffected by digital switching noise on the primary rail. |
| Tracking Power Supply | Battery-Powered IoT Node |
Use Scenario: Generating matched 1.2V and 1.5V rails for DDR memory interface where voltage tracking within ±2% is required during startup and load transients. IC Role / Device Role / Timing Role: Dual-channel regulator with independent ADJ1/ADJ2 feedback enabling precise resistor-ratio matching for tracking accuracy. Use Value: Shared 1.220V reference and matched internal error amplifiers achieve tight inter-rail tracking without external op-amps or complex compensation. | Use Scenario: Long-life sensor node powered by CR2032 coin cell, requiring 3.3V for MCU and 1.8V for BLE radio with multi-year standby life. IC Role / Device Role / Timing Role: Dual LDO managing both active and sleep states: OUT1 powers MCU (120μA IQ), OUT2 powers radio (75μA IQ), each independently shut down. Use Value: Sub-1μA per-channel shutdown current and reverse-current protection extend battery life beyond 5 years in duty-cycled applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7A8300RGRT | Single-channel, 2A output, 4μVRMS noise, 3.3V fixed option only; no dual-output or adjustable capability | Lacks independent second channel and adjustable outputs - unsuitable for asymmetric dual-rail systems | Select only if single-rail, ultra-low-noise, high-current requirement dominates and dual-channel functionality is unnecessary |
| MAX1725EUT+T | Single-channel, 250mA, 1.22V reference, 12μA IQ, no PWRGD or BYP pin; TSSOP-6 package | No dual-channel support, no shutdown control, no noise-reduction bypass - limited to basic low-IQ point-of-load use | Choose only for cost-sensitive, single-rail, non-critical noise applications where footprint and feature set are minimal |
Compared with TPS7A8300RGRT and MAX1725EUT+T, the LT3030IFE#TRPBF uniquely delivers verified dual-channel operation with independent shutdown, PWRGD flags, 20μVRMS noise, and 750mA/250mA asymmetrical current capability - making it the only viable option for compact, battery-powered systems requiring two precisely controlled, low-noise rails.
Availability
LT3030IFE#TRPBF is available at Aetrix Electronics and suitable for battery-powered IoT nodes, microprocessor core/logic supplies, and post-regulators for switching supplies requiring stable component supply, long-term lifecycle support, and guaranteed -40°C to +125°C operation.
Supply support for LT3030IFE#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance analog ICs, emphasizing precision, low noise, and robustness in power management and signal conditioning.
The LT3030IFE#TRPBF belongs to Linear's micropower LDO family, engineered specifically for space-constrained, battery-operated systems demanding dual-rail flexibility, ultra-low quiescent current, and integrated protection without external components.
FAQ
What is the maximum input voltage rating for the LT3030IFE#TRPBF?
The LT3030IFE#TRPBF has an absolute maximum input voltage rating of ±22V on IN1 and IN2 pins. Its operational input voltage range is 1.7V to 20V, supporting applications from single-cell Li-ion batteries to industrial 18V rails. Exceeding 20V during normal operation risks violating the specified electrical characteristics and thermal limits.
Does the LT3030IFE#TRPBF require external capacitors for stability?
Yes, the LT3030IFE#TRPBF requires minimum output capacitance of 10μF for OUT1 and 3.3μF for OUT2, with low ESR ceramic types recommended. Input bypass capacitors (1μF–10μF) are also advised, especially in battery-powered systems where source impedance rises with frequency. Stability is guaranteed across ceramic, tantalum, and aluminum electrolytic types.
How does the PWRGD flag function on the LT3030IFE#TRPBF?
The LT3030IFE#TRPBF provides two open-collector PWRGD flags (PWRGD1 and PWRGD2), each asserting low when its respective output falls below 86% of nominal voltage and releasing (high-impedance) when rising above 90%. An external pull-up resistor is mandatory. The 1.6% hysteresis prevents chatter during marginal regulation conditions.
Can the LT3030IFE#TRPBF operate with independent input supplies?
Yes, the LT3030IFE#TRPBF supports fully independent input supplies on IN1 and IN2, each ranging from 1.7V to 20V. This allows flexible system architectures - such as powering OUT1 from a main battery and OUT2 from a backup rail - while maintaining independent regulation, shutdown, and PWRGD signaling for each channel.
What thermal considerations apply to the LT3030IFE#TRPBF in the 20-lead TSSOP package?
The LT3030IFE#TRPBF in the FE package has θJA = 28°C/W and θJC = 10°C/W, contingent on proper soldering of the exposed pad (Pin 21) to a PCB ground plane. Without thermal pad connection, junction temperature rise exceeds specifications under load. Derating is required above 125°C ambient; continuous operation above TJMAX = 150°C impairs reliability.
LT3030IFE#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Adjustable
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 1.22V
- Voltage - Output (Max):
- 19.5V
- Voltage Dropout (Max):
- 0.48V @ 250mA, 0.48V @ 750mA
- Current - Output:
- 250mA, 750mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 60dB ~ 50dB (120Hz ~ 1MHz)
- Control Features:
- Enable, Power Good
- Protection Features:
- Over Current, Over Temperature, Reverse Polarity
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP-EP
LT3030IFE#TRPBF FAQ
1.How can I place an order for LT3030IFE#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3030IFE#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3030IFE#TRPBF reliable?
The price and inventory of LT3030IFE#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3030IFE#TRPBF is usually 5 days.
3.What payment methods are accepted for LT3030IFE#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT3030IFE#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3030IFE#TRPBF?
LT3030IFE#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3030IFE#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3030IFE#TRPBF?
For technical support, including LT3030IFE#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3030IFE#TRPBF requirements.
6.How does Aetrix verify that LT3030IFE#TRPBF is sourced from the original manufacturer or authorized distributors?
All LT3030IFE#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3030IFE#TRPBF meets industry standards.
7.What is the process for return or replacement of LT3030IFE#TRPBF?
All LT3030IFE#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3030IFE#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3030IFE#TRPBF part is unused and in its original packaging.
Return procedure for LT3030IFE#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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