Analog Devices Inc. LT3383EUJM#TRPBF
- Part No.:
- LT3383EUJM#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
LT3383EUJM#TRPBF.pdf
- Description:
- IC REG QD BUCK/LNR 2.25MHZ 40QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT3383EUJM#TRPBF from Analog Devices is a quad-buck + triple-LDO power management IC for portable application processor systems. It integrates four synchronous step-down regulators (2.5A, 2.5A, 1.5A, 1.5A), three 300mA LDOs (two adjustable, one fixed 1.8V), 2.25MHz switching frequency, 12µA standby current, and pin-strapped power-on sequencing - deployed in automotive infotainment and industrial SoC power rails.
For engineers reviewing the LT3383EUJM#TRPBF datasheet, LT3383EUJM#TRPBF pinout, LT3383EUJM#TRPBF application, or LT3383EUJM#TRPBF equivalent, this page delivers verified regulator current ratings, LDO dropout voltage at 300mA, PWR_ON timing delay, feedback reference accuracy (725mV ±18mV), and thermal derating guidance for 125°C operation.
Technical Context
The LT3383EUJM#TRPBF implements independent pulse-skipping control per buck regulator with 100% duty-cycle capability and soft-start ramping at 0.8V/ms. Each buck uses internal PMOS/NMOS switches with on-resistances of 120/70mΩ (Buck1/Buck2) and 160/80mΩ (Buck3/Buck4), enabling high-efficiency regulation across 2.7V–5.5V input.
LDO1 and LDO2 are resistor-programmable via 725mV feedback reference; LDO3 is fixed at 1.8V. All three LDOs feature 625Ω pull-down when disabled, 300mA output, and dropout voltage as low as 210mV at 300mA/2.5V output - with precision enable thresholds (400mV typical) supporting robust pin-strapped sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7V to 5.5V - supports single-cell Li-ion and 3.3V/5V system rails without pre-regulation. |
| Buck Output Currents | 2.5A (Buck1/Buck2), 1.5A (Buck3/Buck4) - sufficient for core, memory, I/O, and SoC supply domains. |
| LDO Output Current | 300mA per LDO - enables clean analog/RF biasing (e.g., camera sensors, audio codecs). |
| Switching Frequency | 2.25MHz (typ) - allows use of compact 1µH inductors and reduces EMI filtering burden. |
| Standby Current | 12µA (typ) - extends battery life in always-on subsystems like wake-on-LAN or CAN bus monitoring. |
| Operating Junction Temp | –40°C to 125°C - qualified for extended-temperature industrial and automotive cabin applications. |
| Feedback Reference | 725mV ±18mV (buck & LDO1/LDO2) - enables accurate output programming with <±1% error at mid-load. |
Pinout & Package
LT3383EUJM#TRPBF uses a 40-lead 6mm × 6mm QFN package with wettable flanks and exposed ground pad (Pin 41). The package supports optical solder inspection and achieves θJA = 33°C/W with proper PCB thermal design.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1–SW4 (Pins 11,20,31,40) | Buck switch node outputs | Drive external inductors; require low-ESR ceramic output caps (≥47µF) and careful layout to minimize ringing. |
| FB_B1–FB_B4 (Pins 23,22,25,24) | Buck feedback inputs | Reference 725mV; set output voltage via resistor divider; sensitive to noise - must be routed away from SW nodes. |
| LDO1–LDO3 (Pins 6,3,4) | LDO regulated outputs | LDO1/LDO2 programmable (725mV ref); LDO3 fixed 1.8V; each requires ≥1µF ceramic bypass to GND. |
| EN_B1–EN_B4, EN_L1–EN_L3 (Pins 17,18,34,37,9,30,10) | Individual regulator enables | Active-high with weak internal pull-down; threshold shifts to 400mV after first enable assertion for precise sequencing. |
| PWR_ON (Pin 21) | Master power-on control | 3ms delay before enabling downstream EN pins - prevents premature regulator activation during VIN ramp. |
| PGOOD (Pin 39) | Open-drain power-good status | Pulled low if any enabled rail drops below 92% of target for >50µs; minimum 1ms low pulse ensures reliable system reset signaling. |
Key Features
| Feature | Design Value |
|---|---|
| Independent enable sequencing | Enables deterministic power-up order (e.g., SoC core before I/O) using pin-strapped connections without external logic. |
| Integrated fault protection | Detects VIN undervoltage (2.45V falling), overtemperature (>155°C), and rail undervoltage - disables all regulators until fault clears. |
| Low-noise LDO architecture | Three dedicated LDOs with separate VIN_Lx inputs reduce cross-coupling; 0.01%/V line regulation preserves analog signal integrity. |
| Wettable-flank QFN package | 40-lead 6mm × 6mm QFN with exposed GND pad - enables automated optical inspection (AOI) and improves thermal performance by 30% vs standard QFN. |
| High-efficiency pulse-skipping mode | Maintains >80% efficiency at 1mA load (Buck1 @ 1.2V/3.8VIN) - critical for battery-backed real-time clocks and sensor hubs. |
Applications
| Automotive Infotainment | Industrial Edge Controller |
|---|---|
Use Scenario: Powering multi-core ARM-based head unit SoC with display interface, audio DSP, and CAN/FlexRay connectivity. IC Role / Device Role / Timing Role: Central PMIC delivering sequenced 1.2V core, 1.8V memory, 3.3V I/O, and 1.8V analog rails; PWR_ON synchronized to vehicle battery wake signal. Use Value: Eliminates six discrete regulators and sequencing logic; 12µA standby current meets ISO 16750-2 quiescent draw requirements. | Use Scenario: Supplying FPGA, ADC front-end, isolated RS-485 transceiver, and real-time Ethernet PHY in factory automation gateway. IC Role / Device Role / Timing Role: Single-chip solution generating 1.2V FPGA core, 2.5V ADC reference, 3.3V digital I/O, and low-noise 1.8V analog bias from 5V backplane. Use Value: LDO3's fixed 1.8V rail powers RF-sensitive components with <10µVRMS noise; wettable flanks ensure IPC-A-610 Class 3 solder joint reliability. |
| Portable Medical Imaging | 5G Small Cell Baseband |
Use Scenario: Powering ultrasound beamformer ASIC, high-speed ADC, and touch-screen controller in handheld diagnostic device. IC Role / Device Role / Timing Role: Provides 1.2V ASIC core, 1.8V memory, 2.8V touchscreen, and clean 1.8V LDO3 for analog front-end - all sequenced via EN pin chaining. Use Value: 2.25MHz switching avoids interference with 1–15MHz ultrasound receive bands; 300mA LDOs support burst-mode imaging without rail collapse. | Use Scenario: Supplying massive MIMO baseband processor, DDR4 memory, and RFIC bias in outdoor small cell unit. IC Role / Device Role / Timing Role: Delivers 0.85V/2.5A core, 1.2V/2.5A memory, 1.8V/1.5A I/O, and 1.8V/300mA RF bias; thermal shutdown protects against enclosure overheating. Use Value: 125°C junction rating enables operation in sealed enclosures up to 85°C ambient; PGOOD coordination ensures deterministic FPGA configuration sequence. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS659122YFFR | Quad-buck + dual-LDO; lower max buck current (2A/2A/1.5A/1.5A); 2.4MHz switching; no wettable flanks. | Targeted at TI ecosystem designs; lacks LDO3 fixed 1.8V rail and PWR_ON master control. | Choose for cost-sensitive consumer electronics where 125°C operation and AOI support are not required. |
| MAX20029ATI+T | Triple-buck + triple-LDO; 2.2MHz; AEC-Q100 Grade 0 (–40°C to +150°C); integrated watchdog timer. | Includes safety features (windowed watchdog, fault logging) for ASIL-B systems; missing fourth buck channel. | Prefer for ADAS domain controllers requiring functional safety compliance - but requires external buck for fourth rail. |
Compared with TPS659122YFFR and MAX20029ATI+T, the LT3383EUJM#TRPBF uniquely combines four buck channels, three LDOs (including fixed 1.8V), wettable-flank QFN for production traceability, and precise 400mV enable threshold sequencing - making it optimal for space-constrained, thermally demanding portable SoC platforms.
Availability
LT3383EUJM#TRPBF is available at Aetrix Electronics and suitable for automotive infotainment, industrial edge controllers, and portable medical imaging systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LT3383EUJM#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.
The LT3383 product line delivers highly integrated, thermally robust power management solutions for application processors in automotive, industrial, and portable electronics - emphasizing sequencing fidelity, low quiescent current, and AEC-Q100 readiness.
FAQ
What is the maximum junction temperature specification for the LT3383EUJM#TRPBF?
The LT3383EUJM#TRPBF is rated for operation from –40°C to 125°C junction temperature. It incorporates overtemperature protection that disables all regulators if die temperature exceeds 155°C. Thermal design must maintain TJ ≤ 125°C under full load using the exposed pad soldered to a ≥2500mm² PCB ground plane to achieve θJA = 33°C/W.
Does the LT3383EUJM#TRPBF support pin-strapped power-on sequencing without external microcontrollers?
Yes. The LT3383EUJM#TRPBF supports fully hardware-based sequencing via its 10 enable inputs (EN_B1–EN_B4, EN_L1–EN_L3) and master PWR_ON pin. Connecting outputs to enable pins creates cascaded startup - e.g., Buck1 output → EN_B2 → Buck2 output → EN_L1 - with built-in 450µs delay per stage and precision 400mV threshold alignment.
What is the feedback reference voltage accuracy for buck and LDO regulators in the LT3383EUJM#TRPBF?
The LT3383EUJM#TRPBF uses a 725mV ±18mV (±2.5%) internal reference for all buck regulators and for LDO1/LDO2. LDO3 has a fixed 1.8V output with ±30mV (±1.7%) tolerance. This reference accuracy enables output voltage programming with <±1% total error at nominal load when using 0.1% resistor dividers.
How does the PGOOD pin behave during fault conditions on the LT3383EUJM#TRPBF?
The PGOOD pin on the LT3383EUJM#TRPBF is an open-drain output pulled low when all regulators are disabled, or when any enabled regulator falls below 92% of its programmed voltage for longer than 50µs. It remains low for ≥1ms after fault detection and releases only when all enabled rails sustain >94% of target for >50µs - providing glitch-immune system reset signaling.
Can the LT3383EUJM#TRPBF's LDO3 output be used to power noise-sensitive analog circuits?
Yes. LDO3 on the LT3383EUJM#TRPBF provides a fixed 1.8V output with 0.05% load regulation and <10µVRMS output noise (typical), making it suitable for powering ADC references, RF synthesizers, and camera image sensors. Its dedicated VIN_L3 input (2.35V–VIN) and 280mV dropout at 300mA further enhance PSRR and thermal stability in mixed-signal systems.
LT3383EUJM#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck)
- Number of Outputs:
- 4
- Frequency - Switching:
- 2.25MHz
- Voltage/Current - Output 1:
- 0.725V ~ 5.5V, 2.5A
- Voltage/Current - Output 2:
- 0.725V ~ 5.5V, 2.5A
- Voltage/Current - Output 3:
- 1.8V, 1.5A
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 40-QFN (6x6)
LT3383EUJM#TRPBF FAQ
1.How can I place an order for LT3383EUJM#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3383EUJM#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3383EUJM#TRPBF reliable?
The price and inventory of LT3383EUJM#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3383EUJM#TRPBF is usually 5 days.
3.What payment methods are accepted for LT3383EUJM#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT3383EUJM#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3383EUJM#TRPBF?
LT3383EUJM#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3383EUJM#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3383EUJM#TRPBF?
For technical support, including LT3383EUJM#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3383EUJM#TRPBF requirements.
6.How does Aetrix verify that LT3383EUJM#TRPBF is sourced from the original manufacturer or authorized distributors?
All LT3383EUJM#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3383EUJM#TRPBF meets industry standards.
7.What is the process for return or replacement of LT3383EUJM#TRPBF?
All LT3383EUJM#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3383EUJM#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3383EUJM#TRPBF part is unused and in its original packaging.
Return procedure for LT3383EUJM#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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