My Inquiry
My Account
Analog Devices Inc. LT3581EDE#PBF
- Part No.:
- LT3581EDE#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 14-WFDFN Exposed Pad
- Datasheet:
-
LT3581EDE#PBF.pdf
- Description:
- IC REG BST CHARGE PUMP ADJ 14DFN
- Quantity:
- Payment:
- Shipping:
Inventory:252
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LT3581EDE#PBF from Analog Devices (formerly Linear Technology) is a 3.3A, 42V combined master/slave PWM DC/DC converter IC optimized for boost, inverting, SEPIC, and flyback topologies with integrated fault protection. It delivers 12V at 830mA or –12V at 625mA from a 5V input, features 2.5MHz max switching frequency, output short-circuit protection, and operates across –40°C to 125°C. It is used in local power supplies requiring robust overvoltage, overcurrent, and overtemperature protection.
For engineers reviewing the LT3581EDE#PBF datasheet, LT3581EDE#PBF pinout, LT3581EDE#PBF application, or LT3581EDE#PBF equivalent, key selection criteria include its dual-switch current sharing (1.9A/1.4A), 250mV typical VCE(SAT) at 2.75A, user-configurable UVLO via SHDN pin, and compatibility with high-frequency layout (2MHz operation in DFN package).
Technical Context
The LT3581EDE#PBF implements constant-frequency current-mode control with internal ramp compensation and dual NPN power switches-master (SW1) and slave (SW2)-that can be paralleled for 3.3A total current limit. Its fault detection logic monitors VIN overvoltage (>22V), SW node overvoltage (>42V), die temperature (>165°C), and switch overcurrent using sample-mode sampling during regulation loss.
It supports flexible timing: free-running via RT-to-ground resistor (200kHz–2.5MHz), external synchronization via SYNC pin (1.3V high threshold), and buffered clock output on CLKOUT for multi-IC synchronization. The GATE pin provides linearly SS-voltage-controlled PMOS pull-down current (up to 933µA) for controlled output disconnect during faults.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Configuration | Dual NPN: 1.9A master (SW1) + 1.4A slave (SW2), tied for 3.3A combined current limit with 78% current sharing ratio |
| Input Voltage Range | 2.5V to 22V operating; 40V absolute max transient - enables direct connection to automotive 12V or industrial 24V rails with transient margin |
| Switching Frequency | 200kHz to 2.5MHz adjustable via RT pin or external SYNC - supports compact magnetics and EMI spread-spectrum design |
| VCE(SAT) | 250mV typical at 2.75A with both switches tied - reduces conduction loss and thermal stress in high-current boost/inverting designs |
| Fault Protection | Detects output short, VIN >22V, SW1/SW2 >42V, TJ >165°C, and external FAULT assertion - triggers automatic shutdown and soft-recovery sequence |
| Soft-Start Control | SS pin charges via internal 250kΩ to ~2.1V; GATE pull-down current scales linearly with SS voltage up to 933µA - enables controlled inrush limiting and hot-swap capability |
| Package & Temp Range | 14-pin 4mm × 3mm DFN with exposed pad (Pin 15 = GND); rated for –40°C to +125°C junction temperature |
Pinout & Package
LT3581EDE#PBF is housed in a 14-pin plastic DFN (4mm × 3mm) with exposed thermal pad (Pin 15) soldered to PCB ground for thermal management and EMI reduction. Pin pitch is 0.5mm; recommended reflow profile complies with JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1 (Pins 6,7) | Master NPN collector | Primary high-current switching node; must use minimal trace area to reduce EMI and parasitic inductance |
| SW2 (Pins 8,9) | Slave NPN collector | Secondary switch enabling current sharing; tied to SW1 for 3.3A mode or used independently for dual-output topologies |
| FB (Pin 1) | Feedback input | Accepts positive (1.215V reference) or negative (9mV reference) feedback for boost/inverting configurations; bias current 83.3µA |
| VC (Pin 2) | Error amplifier output | Connects to external compensation network (R-C-RC) to stabilize loop response across load/line variations |
| GATE (Pin 3) | PMOS gate drive | Sinks current up to 933µA (SS-dependent); used for external PMOS disconnect during fault or sequencing |
| FAULT (Pin 4) | Bidirectional fault indicator | Active-low open-drain output; pulled low internally on fault or externally to force shutdown and initiate recovery sequence |
| VIN (Pin 5) | Main input supply | Requires local ceramic bypass (≥4.7µF); supports 2.5V–22V operation with 40V transient rating |
| CLKOUT (Pin 10) | Buffered oscillator output | Drives ≤50pF load; provides synchronized clock for other regulators and linear junction temperature monitoring via duty cycle |
| SHDN (Pin 11) | Enable/disable control | High-threshold (1.33V typ.) with 30mV hysteresis; accepts slow-ramping signals and configures UVLO via resistor divider |
| RT (Pin 12) | Frequency setting | Resistor-to-ground sets free-running frequency (e.g., 43.2kΩ → 2MHz); floating not allowed |
| SS (Pin 13) | Soft-start timing | Charged by internal 250kΩ; controls ramp rate of switch current and GATE pull-down for inrush limiting |
| SYNC (Pin 14) | External clock input | Accepts 0.4V–1.3V logic levels; overrides internal oscillator when driven; <0.4V reverts to free-run mode |
| GND (Pin 15) | Power and signal ground | Exposed thermal pad; must be soldered to solid PCB ground plane for thermal dissipation and noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual-switch architecture | Enables single-chip 3.3A boost/inverting conversion without external MOSFETs - reduces BOM count and layout complexity |
| Output short-circuit protection with auto-recovery | Uses sample-mode current sensing and SS-timed timeout to clear faults without manual reset - improves system reliability in unattended applications |
| Configurable undervoltage lockout (UVLO) | SHDN pin supports external resistor divider to set precise VIN turn-on threshold (e.g., 6V or 9V), preventing brownout operation |
| High-frequency synchronization capability | CLKOUT and SYNC pins allow precise phase alignment across multiple converters - critical for noise-sensitive imaging or RF subsystems |
| Thermal-aware clock output | CLKOUT duty cycle varies linearly with junction temperature - eliminates need for external thermal sensor in space-constrained designs |
| Low-quiescent-current shutdown | Consumes ≤1µA in shutdown (VSHDN = 0V) - extends battery life in portable or always-on monitoring systems |
Applications
| Vacuum Fluorescent Display (VFD) Bias Supply | TFT-LCD Panel Bias Supply |
|---|---|
Use Scenario: Generating stable ±12V to ±30V bias rails for VFD anode and grid drivers in automotive instrument clusters and industrial HMIs. IC Role / Device Role / Timing Role: LT3581EDE#PBF operates in inverting configuration to produce negative high-voltage rail; uses sample-mode fault detection to survive display arcing events. Use Value: Integrated 42V switches and output short protection eliminate need for external TVS or crowbar circuits, reducing solution size by 35% vs discrete alternatives. |
Use Scenario: Providing AVDD (12V–18V) and VGL (–5V to –10V) supplies for TFT-LCD source/gate drivers in medical displays and avionics panels. IC Role / Device Role / Timing Role: LT3581EDE#PBF configured as dual-output SEPIC or independent boost/inverting channels; CLKOUT synchronizes with display timing controller to suppress beat frequencies. Use Value: 2.5MHz switching enables use of 1µH inductors and 10µF ceramic output caps - achieves <1mm profile and <5mVpp ripple under dynamic load steps. |
| Automotive Engine Control Unit (ECU) Local Power | Industrial Programmable Logic Controller (PLC) I/O Module Supply |
Use Scenario: Generating isolated 5V or 3.3V auxiliary rails from noisy 12V vehicle battery in engine bay ECUs, surviving load dump transients up to 40V. IC Role / Device Role / Timing Role: LT3581EDE#PBF used in boost configuration with external PMOS disconnect (GATE-driven); UVLO set to 6.5V to prevent restart during cranking. Use Value: Built-in 40V transient tolerance and VIN OVLO (>22V) eliminate need for upstream TVS or LDO pre-regulator - simplifies front-end design and improves efficiency by 12%. |
Use Scenario: Powering isolated analog front-ends and digital isolators in modular PLC I/O cards where field-side 24V supply must be converted to clean 5V/3.3V with fault containment. IC Role / Device Role / Timing Role: LT3581EDE#PBF configured as flyback with optocoupler feedback; FAULT pin interfaces directly with PLC safety monitor logic for immediate channel disable. Use Value: Dual-fault reporting (FAULT1 internal / FAULT2 external) enables SIL2-compliant diagnostics; GATE-controlled PMOS ensures galvanic isolation integrity during fault conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-switch DC/DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT3573EFE#PBF | Single 3.25A switch, no slave switch; 40V max switch voltage; no built-in sample-mode short-circuit detection | Lacks dual-switch flexibility and output short protection - requires external circuitry for VFD/LCD bias fault handling | Select when only single-rail boost is needed and board space allows discrete protection components |
| MAX17595ATP+T | 3A synchronous buck-boost controller (external FETs); supports 4.5V–60V input; no integrated switches or fault latching | Requires 4 external MOSFETs and complex layout; no native inverting or flyback support without transformer redesign | Choose for wide-input industrial supplies where efficiency >94% and thermal headroom outweigh integration benefits |
Compared with LT3581EDE#PBF, LT3573EFE#PBF offers lower cost but sacrifices fault robustness and topology flexibility, while MAX17595ATP+T delivers higher efficiency at the expense of bill-of-materials complexity and design validation effort.
Availability
LT3581EDE#PBF is available at Aetrix Electronics and suitable for vacuum fluorescent display (VFD) bias supplies, TFT-LCD panel power, and automotive ECU local power applications requiring stable component supply, long-term lifecycle assurance, and AEC-Q200-aligned reliability.
Supply support for LT3581EDE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full technical and manufacturing continuity for all Linear power products. Linear Technology pioneered high-performance analog ICs with emphasis on precision, ruggedness, and ease of use.
The LT3581EDE#PBF belongs to Linear's high-voltage monolithic DC/DC converter family, designed specifically for space-constrained, fault-prone power nodes in automotive, industrial, and display electronics where integration, protection, and thermal resilience are critical.
FAQ
What is the maximum supported switching frequency for LT3581EDE#PBF?
The LT3581EDE#PBF supports a switching frequency range of 200kHz to 2.5MHz. At the upper end, a 34kΩ resistor from RT to GND sets fSW ≈ 2.5MHz (typical), enabling compact magnetic design and reduced output capacitance. Operation above 2.5MHz is not guaranteed and may compromise fault protection timing margins.
How does LT3581EDE#PBF detect and respond to an output short circuit?
The LT3581EDE#PBF detects output shorts via sample-mode current sensing: when FB voltage deviates >3.7% from regulation (e.g., <45mV for inverting mode), it forces Q1/Q2 on briefly each cycle to measure peak inductor current. If sampled current exceeds 1.9A (SW1) or 3.3A (combined), FAULT pin pulls low, GATE goes high-Z, and SS initiates a timed recovery sequence before automatic restart.
Can LT3581EDE#PBF be used in flyback configuration, and what is required?
Yes, LT3581EDE#PBF supports flyback topology using SW1 as primary switch and optional optocoupler feedback to FB. A transformer with appropriate turns ratio, snubber network across primary, and secondary-side rectification/filtering are required. The datasheet Figure 10 provides a validated 5V@1A flyback design with 85% efficiency at 12V input.
What is the purpose of the GATE pin on LT3581EDE#PBF, and how is it controlled?
The GATE pin on LT3581EDE#PBF sinks current (0–933µA) to drive the gate of an external PMOS transistor for output disconnect. Its current scales linearly with SS pin voltage - at SS ≥ 500mV, GATE delivers full current to fully turn on the PMOS. This enables controlled hot-swap, inrush limiting, and fault-isolation without additional driver ICs.
Does LT3581EDE#PBF require external compensation, and where is it connected?
Yes, LT3581EDE#PBF requires external Type II or Type III compensation connected between VC (Pin 2) and GND. A standard network includes series RC from VC to FB and parallel capacitor from VC to GND. Component values depend on topology, switching frequency, and output filter - the datasheet Appendix provides design equations and stability guidelines.
LT3581EDE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 14-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive or Negative
- Topology:
- Boost, Charge Pump, Cuk, Flyback, SEPIC
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 22V
- Voltage - Output (Min/Fixed):
- 1.215V
- Voltage - Output (Max):
- 42V (Switch)
- Current - Output:
- 3.3A (Switch)
- Frequency - Switching:
- 200kHz ~ 2.5MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-DFN (4x3)
LT3581EDE#PBF FAQ
1.How can I place an order for LT3581EDE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3581EDE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3581EDE#PBF reliable?
The price and inventory of LT3581EDE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3581EDE#PBF is usually 5 days.
3.What payment methods are accepted for LT3581EDE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT3581EDE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3581EDE#PBF?
LT3581EDE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3581EDE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3581EDE#PBF?
For technical support, including LT3581EDE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3581EDE#PBF requirements.
6.How does Aetrix verify that LT3581EDE#PBF is sourced from the original manufacturer or authorized distributors?
All LT3581EDE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3581EDE#PBF meets industry standards.
7.What is the process for return or replacement of LT3581EDE#PBF?
All LT3581EDE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3581EDE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3581EDE#PBF part is unused and in its original packaging.
Return procedure for LT3581EDE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LT3581EDE#PBF Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
