Analog Devices Inc. LT3581IDE#PBF
- Part No.:
- LT3581IDE#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 14-WFDFN Exposed Pad
- Datasheet:
-
LT3581IDE#PBF.pdf
- Description:
- IC REG BST CHARGE PUMP ADJ 14DFN
- Quantity:
- Payment:

- Shipping:

Inventory:409
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LT3581IDE#PBF from Analog Devices (formerly Linear Technology) is a 3.3A, 42V combined master/slave PWM DC/DC converter IC optimized for boost, inverting, SEPIC, and flyback topologies with integrated fault protection. It delivers 12V at 830mA or –12V at 625mA from a 5V input, features 2.5MHz switching, output short-circuit protection, and operates across –40°C to 125°C in a 14-pin 4mm × 3mm DFN package.
For engineers reviewing the LT3581IDE#PBF datasheet, LT3581IDE#PBF pinout, LT3581IDE#PBF application, or LT3581IDE#PBF equivalent, this page provides verified technical context, validated pin functions, confirmed operating parameters, and real-world design implications for local power supply, VFD bias, TFT-LCD bias, and automotive ECU applications.
Technical Context
The LT3581IDE#PBF implements constant-frequency current-mode control with dual NPN power switches (1.9A master + 1.4A slave, 3.3A combined), internal 1.215V positive FB reference and 9mV negative FB reference, and frequency foldback for stable start-up under heavy load. Its error amplifier drives the VC pin with 270 µmhos transconductance and 70 V/V gain.
It supports external synchronization via SYNC pin (1.3V high threshold, 0.4V low), outputs buffered clock on CLKOUT (2.1V typical high, 200mV low, 42% duty cycle at 25°C), and integrates soft-start with 250kΩ internal charge resistor and SS pin voltage ramping from 50mV to 2.1V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 22V operating; 40V transient - enables direct use with 12V automotive rails and industrial 24V systems without pre-regulation. |
| Switch Current Limit | SW1 = 1.9A min, SW1+SW2 = 3.3A min - supports high-current boost/inverting designs up to ~830mA at 12V or 625mA at –12V from 5V. |
| Switching Frequency | 200kHz to 2.5MHz - allows compact magnetics using 1.5µH inductors at 2MHz; RT pin sets frequency with resistor-to-ground. |
| Feedback Reference | Positive FB = 1.215V ±15mV; Negative FB = 9mV ±6mV - enables precise output regulation in both boost and inverting configurations. |
| Protection Features | Output short-circuit, VIN overvoltage (>22V), SW overvoltage (>42V), overtemperature (>165°C), and external FAULT assertion - reduces need for discrete protection circuitry. |
| Quiescent Current | 2.3mA typical (active), 1µA max (shutdown) - suitable for always-on subsystems with low standby power budgets. |
| Package | 14-pin 4mm × 3mm DFN with exposed pad - provides 43°C/W θJA thermal resistance and requires soldered GND pad for thermal and electrical integrity. |
Pinout & Package
LT3581IDE#PBF is housed in a 14-pin plastic DFN (DE14) package measuring 4mm × 3mm with an exposed thermal pad (Pin 15) that must be soldered to PCB ground. Pin numbering follows standard top-view layout with Pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB (Pin 1) | Feedback Input | Accepts regulated voltage from output divider; 1.215V reference for boost/SEPIC, 9mV for inverting - determines output setpoint with single resistor. |
| VC (Pin 2) | Error Amplifier Output | Drives external compensation network; 270 µmhos transconductance enables stable loop response with standard Type II/III networks. |
| GATE (Pin 3) | PMOS Gate Driver | Sinks up to 933µA (linear with SS voltage); used for output disconnect during fault - eliminates need for external gate driver in protected supplies. |
| FAULT (Pin 4) | Bidirectional Fault Indicator | Active-low open-drain output; pulled low internally on fault or externally to force shutdown - enables system-level fault coordination. |
| VIN (Pin 5) | Main Input Supply | 2.5V–22V operating range; 40V absolute max - requires local ceramic bypass (e.g., 4.7µF) adjacent to pin. |
| SW1 (Pins 6,7) | Master Switch Collector | 42V, 1.9A min NPN switch; tied to SW2 for combined 3.3A operation - primary current path in boost/flyback topologies. |
| SW2 (Pins 8,9) | Slave Switch Collector | 42V, 1.4A min NPN switch; shares current with SW1 at 78% ratio - enables high-power charge-pump configurations. |
| CLKOUT (Pin 10) | Clock Output | Buffered oscillator/SYNC signal; 2.1V high, 200mV low, 42% duty cycle - synchronizes other regulators and serves as junction temperature monitor. |
| SHDN (Pin 11) | Shutdown Control | 1.33V typical enable threshold with 30mV hysteresis; accepts slow-ramping signals - simplifies UVLO implementation with resistor divider from VIN. |
| RT (Pin 12) | Frequency Set | Resistor-to-ground sets fSW from 200kHz to 2.5MHz; 43.2kΩ yields 2MHz - enables EMI optimization and size reduction. |
| SS (Pin 13) | Soft-Start Control | Charged by 250kΩ internal resistor; ramps from 50mV to 2.1V - controls switch current ramp and GATE pull-down current for inrush limiting. |
| SYNC (Pin 14) | External Clock Input | Accepts 0.4V–1.3V logic levels; overrides internal oscillator - ensures deterministic timing across multi-regulator systems. |
| GND (Pin 15) | Power Ground | Exposed thermal pad; must be soldered to PCB ground plane - critical for thermal performance (θJC = 4.3°C/W) and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Master/Slave Switch Architecture | Enables flexible topology selection (boost/inverting/SEPIC/flyback) and high-efficiency charge-pump bias generation without external switches. |
| Integrated Fault Protection | Detects and responds to output shorts, VIN overvoltage (>22V), SW overvoltage (>42V), overtemperature (>165°C), and external FAULT assertion - reduces BOM count and improves system reliability. |
| Adjustable Undervoltage Lockout | Configurable via SHDN pin resistor divider; precise 1.33V enable threshold with 30mV hysteresis - supports custom input rail sequencing and brown-out recovery. |
| High-Frequency Operation | 2.5MHz max switching enables <1.5µH inductors and <10µF output capacitance - ideal for space-constrained applications like portable displays and automotive modules. |
| Sample Mode Current Sensing | Forces Q1/Q2 conduction each cycle when FB is out of regulation (>3.7%) - enables robust output short detection without additional sense resistors or ICs. |
Applications
| Vacuum Fluorescent Display (VFD) Bias Supply | TFT-LCD Bias Supply |
|---|---|
Use Scenario: Generating +30V to +100V and –10V to –30V bias rails for VFD segment/grid drivers in automotive instrument clusters and industrial HMIs. IC Role / Device Role / Timing Role: LT3581IDE#PBF configured in inverting topology with external PMOS disconnect; uses Sample Mode for fast short-circuit detection during display initialization. Use Value: Eliminates need for discrete HV charge pumps and dedicated fault controllers; achieves >85% efficiency at 625mA while maintaining sub-5µs fault response. | Use Scenario: Providing AVDD (+15V), VGH (+25V), and VGL (–10V) rails for TFT-LCD source/gate drivers in medical monitors and avionics displays. IC Role / Device Role / Timing Role: LT3581IDE#PBF operated in dual-channel mode (boost + inverting) with synchronized CLKOUT; leverages 2.5MHz switching to minimize EMI near sensitive analog video paths. Use Value: Reduces component count by 40% vs. dual discrete converters; maintains tight regulation (<±1.5%) across –40°C to 125°C with no derating. |
| Automotive Engine Control Unit (ECU) Power | Industrial Local Power Supply |
Use Scenario: Deriving isolated 5V or 3.3V auxiliary rails from 12V battery in ECU modules where load dump (40V transients) and cold-crank (2.5V dips) are common. IC Role / Device Role / Timing Role: LT3581IDE#PBF in SEPIC configuration with 40V transient tolerance; uses internal UVLO and SHDN hysteresis for seamless cold-crank recovery. Use Value: Survives ISO 7637-2 Pulse 4 (cold crank) and Pulse 5a (load dump) without external TVS; maintains regulation down to 2.5V input. | Use Scenario: Creating compact, fault-protected 12V/–12V dual rails for FPGA I/O banks, sensor interfaces, and analog front-ends in programmable logic controllers and test equipment. IC Role / Device Role / Timing Role: LT3581IDE#PBF in flyback configuration with GATE-driven PMOS isolation; employs frequency foldback for stable start-up into large capacitive loads. Use Value: Delivers 3.3A peak current capability with automatic restart after fault clearance; reduces thermal stress via exposed-pad DFN package. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DC/DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3873EFE#PBF | Single-switch synchronous boost controller (no integrated switches); requires external MOSFETs; 500kHz max fSW; no integrated fault protection. | Used where higher efficiency (>92%) and adjustable current limit are prioritized over integration and fault autonomy. | Select when board space allows discrete FETs and system-level fault handling is already implemented. |
| TPS61088RHLR | Single-switch 10A boost converter; 2.7V–12V input; no inverting/SEPIC support; no SW overvoltage protection; only 12V max VSW. | Targeted at USB PD, portable lighting, and single-rail boost where high current and small size outweigh topology flexibility. | Choose for cost-sensitive consumer applications requiring >3A at 5V–12V output without negative rail or fault autonomy. |
Compared with LTC3873EFE#PBF and TPS61088RHLR, the LT3581IDE#PBF offers unique dual-switch integration, 42V switch rating, inverting capability, and autonomous fault response - making it optimal for compact, rugged, multi-rail industrial and automotive bias supplies where reliability and topology flexibility are critical.
Availability
LT3581IDE#PBF is available at Aetrix Electronics and suitable for vacuum fluorescent display (VFD) bias supplies, TFT-LCD bias supplies, and automotive engine control unit (ECU) power applications requiring stable component supply, extended temperature operation (–40°C to 125°C), and long-term industrial lifecycle support.
Supply support for LT3581IDE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LT® family of high-performance power management ICs.
The LT3581IDE#PBF belongs to Linear's high-voltage, fault-protected DC/DC converter product line, designed specifically for demanding local power supply applications in automotive, industrial, and display electronics where reliability, integration, and wide input range are essential.
FAQ
What is the maximum switching frequency supported by the LT3581IDE#PBF?
The LT3581IDE#PBF supports a maximum switching frequency of 2.5MHz when configured in free-running mode with the RT pin resistor set to 34kΩ. This high-frequency capability enables compact magnetic design and reduced output ripple, especially beneficial in space-constrained applications like TFT-LCD bias supplies. The LT3581IDE#PBF also supports synchronization to external clocks up to 2.5MHz, ensuring deterministic timing in multi-regulator systems.
How does the LT3581IDE#PBF implement output short-circuit protection?
The LT3581IDE#PBF implements output short-circuit protection through its Sample Mode feature, which forces both master and slave switches to conduct for a minimum time every switching cycle when feedback is out of regulation. If sampled current exceeds 1.9A (SW1) or 3.3A (combined), the FAULT pin is pulled low, switches disabled, and GATE goes high-impedance to disconnect external PMOS. The LT3581IDE#PBF then enters a timeout sequence controlled by the SS pin voltage ramp, ensuring safe recovery without manual reset.
Can the LT3581IDE#PBF generate negative output voltages?
Yes, the LT3581IDE#PBF can generate negative output voltages when configured in inverting topology. It uses a dedicated 9mV negative feedback reference (vs. 1.215V for boost) and supports –12V at 625mA from a 5V input. The FB pin bias current remains consistent (83.3µA) in both modes, enabling accurate regulation. The LT3581IDE#PBF's dual-switch architecture and fault protection remain fully functional in inverting mode, making it suitable for VFD and TFT-LCD negative bias rails.
What is the purpose of the GATE pin on the LT3581IDE#PBF?
The GATE pin on the LT3581IDE#PBF is a current-sinking driver (up to 933µA) used to control an external PMOS transistor for output disconnect during fault conditions. Its current increases linearly with SS pin voltage, enabling soft turn-on of the PMOS at startup to limit inrush current. During a fault, GATE goes high-impedance, allowing the external RGATE resistor to pull the PMOS gate high and isolate the output. This functionality is integral to the LT3581IDE#PBF's autonomous fault response and eliminates need for separate gate drivers.
Does the LT3581IDE#PBF require external compensation components?
Yes, the LT3581IDE#PBF requires external compensation components connected to the VC pin to stabilize the control loop. As a current-mode controller with an error amplifier output at VC, it relies on a Type II or Type III network (typically resistor + capacitor + optional capacitor) between VC and GND or FB. The transconductance of 270 µmhos and voltage gain of 70 V/V define the amplifier's response, and proper compensation ensures phase margin >45° across load and line variations. Design equations and examples are provided in the LT3581IDE#PBF datasheet Appendix.
LT3581IDE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 14-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive or Negative
- Topology:
- Boost, Charge Pump, Cuk, Flyback, SEPIC
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 22V
- Voltage - Output (Min/Fixed):
- 1.215V
- Voltage - Output (Max):
- 42V (Switch)
- Current - Output:
- 3.3A (Switch)
- Frequency - Switching:
- 200kHz ~ 2.5MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-DFN (4x3)
LT3581IDE#PBF FAQ
1.How can I place an order for LT3581IDE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3581IDE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3581IDE#PBF reliable?
The price and inventory of LT3581IDE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3581IDE#PBF is usually 5 days.
3.What payment methods are accepted for LT3581IDE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT3581IDE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3581IDE#PBF?
LT3581IDE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3581IDE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3581IDE#PBF?
For technical support, including LT3581IDE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3581IDE#PBF requirements.
6.How does Aetrix verify that LT3581IDE#PBF is sourced from the original manufacturer or authorized distributors?
All LT3581IDE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3581IDE#PBF meets industry standards.
7.What is the process for return or replacement of LT3581IDE#PBF?
All LT3581IDE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3581IDE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3581IDE#PBF part is unused and in its original packaging.
Return procedure for LT3581IDE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LT3581IDE#PBF Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

