Analog Devices Inc. LT3582EUD-12#PBF
- Part No.:
- LT3582EUD-12#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
LT3582EUD-12#PBF.pdf
- Description:
- IC REG BUCK BOOST 12V DL 16QFN
- Quantity:
- Payment:

- Shipping:

Inventory:283
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LT3582EUD-12#PBF from Analog Devices (formerly Linear Technology) is a dual monolithic DC/DC converter IC integrating a boost and an inverting regulator with factory-programmed ±12V outputs, 2.55V–5.5V input range, integrated power switches, and built-in output disconnect. It delivers up to 80mA positive and 85mA negative output current in a compact 16-pin 3mm × 3mm QFN package, targeting AMOLED and CCD bias supplies.
For engineers reviewing the LT3582EUD-12#PBF datasheet, LT3582EUD-12#PBF pinout, LT3582EUD-12#PBF application, or LT3582EUD-12#PBF equivalent, key selection criteria include its fixed ±12V dual-rail generation, shutdown quiescent current of 0.01μA, integrated soft-start ramp control via RAMPP/RAMPN pins, and compatibility with 5V input systems requiring isolated bipolar supplies without external feedback resistors.
Technical Context
The LT3582EUD-12#PBF implements two independent switching regulators: a boost converter with NMOS switch (350mA current limit) generating +12V, and an inverting converter with PMOS switch (600mA current limit) generating –12V - both using single-inductor topologies and sharing no magnetic coupling. Its control architecture dynamically adjusts peak inductor current and switch off-time to maintain regulation across load currents while minimizing output ripple.
Unlike the programmable LT3582 variant, the LT3582EUD-12#PBF has OTP memory permanently configured for ±12V outputs, simultaneous power-up sequencing (PUSEQ = 11), enabled power-down discharge (PDDIS = 1), and fixed 1μA ramp current - eliminating I2C interface dependency. All feedback dividers, output disconnect, and soft-start timing are internal and non-adjustable.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltages | Fixed +12V and –12V outputs; no external resistor network required |
| Input Voltage Range | 2.55V to 5.5V - supports direct operation from USB 5V or Li-ion battery rails |
| Boost Switch Current Limit | 350mA typical - sets maximum deliverable +12V output current under short-circuit or overload |
| Inverting Switch Current Limit | 600mA typical - defines maximum deliverable –12V output current capability |
| Quiescent Current | 325μA active mode / 0.01μA shutdown - enables ultra-low-power standby in portable imaging systems |
| Package | 16-pin 3mm × 3mm QFN with exposed thermal pad - supports high-density PCB layout and thermal dissipation up to 125°C junction |
| Operating Temperature | –40°C to +125°C - qualified for industrial and automotive display power applications |
Pinout & Package
LT3582EUD-12#PBF is housed in a 16-pin plastic QFN (3mm × 3mm) with exposed thermal pad (Pin #17, GND). The package requires soldering the exposed pad to a PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CA (1) | I²C Address Select | Configures slave address (0110001 or 1000101); tied to GND or VIN - unused in LT3582EUD-12#PBF but must be terminated |
| VOUTN (2) | Negative Output | Regulated –12V output node; requires local ceramic decoupling to GND |
| SWN (3,4) | Inverting Switch Node | Drain of internal PMOS; connects to inductor - low-inductance routing critical for EMI control |
| VIN (5) | Input Supply | Main 2.55–5.5V supply input; bypassed with ceramic capacitor near pin |
| RAMPN (6) | Inverting Soft-Start Ramp | Charged by fixed 1μA current; capacitor value sets –12V output ramp rate during startup |
| RAMPP (7) | Boost Soft-Start Ramp | Charged by fixed 1μA current; capacitor value sets +12V output ramp rate during startup |
| SHDN (8) | Shutdown Control | Active-high enable (VIH ≥ 1.1V); integrates 222kΩ pull-down - enables system-level power sequencing |
| VOUTP (9) | Boost Output Disconnect Node | +12V output with integrated PMOS disconnect; discharges to GND when disabled |
| CAPP (10,11) | Boost Capacitor Node | Connects to boost output capacitor; floats near VIN during shutdown |
| SWP (12) | Boost Switch Node | Drain of internal NMOS; connects to boost inductor - minimize trace area for EMI reduction |
| GND (13) | Ground Reference | Analog/digital ground return; must connect to low-impedance PCB ground plane |
| VPP (14) | OTP Programming Voltage | 13–15V input for OTP write; unused in LT3582EUD-12#PBF - leave floating or bypassed |
| SDA (15) | I²C Data Line | Bidirectional data pin; must be pulled to GND or VIN if I²C unused per datasheet |
| SCL (16) | I²C Clock Line | Serial clock input; must be pulled to GND or VIN if I²C unused |
Key Features
| Feature | Design Value |
|---|---|
| Dual-output ±12V generation | Single-chip solution eliminates need for discrete inverting charge pump or dual-controller design |
| Integrated output disconnect | PMOS switch isolates VOUTP from boost circuit during shutdown, enabling controlled discharge |
| Factory-configured power-up sequencing | Simultaneous +12V/–12V ramp-up (PUSEQ = 11) ensures balanced rail startup for sensitive analog circuits |
| Power-down discharge | Internal transistors actively sink current from both outputs during shutdown - prevents latch-up in downstream circuitry |
| No external feedback resistors | Reduces BOM count, layout area, and voltage-divider drift errors inherent in adjustable converters |
Applications
| AMOLED Display Bias | CCD Image Sensor Power |
|---|---|
Use Scenario: Generating stable ±12V bias rails for active-matrix organic LED pixel drivers and gate line drivers. IC Role / Device Role / Timing Role: Dual-rail DC/DC converter providing regulated, low-noise, sequenced outputs for display panel power management. Use Value: Eliminates need for separate boost and inverting ICs, reduces board space by >40%, and ensures matched startup timing to prevent display artifacts. |
Use Scenario: Supplying precision ±12V analog bias to CCD image sensor arrays in medical or scientific cameras. IC Role / Device Role / Timing Role: Fixed-output dual converter delivering low-ripple, thermally stable rails synchronized for analog front-end operation. Use Value: Maintains <±0.5% output accuracy over –40°C to +125°C, enabling consistent sensor gain calibration without external trimming. |
| Industrial Instrumentation | Portable Test Equipment |
Use Scenario: Powering op-amp-based signal conditioning stages requiring clean dual supplies in PLC analog I/O modules. IC Role / Device Role / Timing Role: Compact, high-efficiency dual converter supplying isolated ±12V for rail-to-rail input/output amplifiers. Use Value: Achieves >85% efficiency at 50mA load, reducing thermal load in sealed enclosures and extending mean time between failures. |
Use Scenario: Providing dual-rail power in handheld oscilloscopes or spectrum analyzers where battery life and size are critical. IC Role / Device Role / Timing Role: Low-quiescent-current DC/DC source enabling <1μA system standby with fast wake-up from shutdown. Use Value: 0.01μA shutdown current extends lithium-polymer battery runtime by >3× versus comparable adjustable solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC/DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT3582EUD-5#PBF | Factory-programmed for ±5V outputs; identical pinout, package, and feature set | Targets low-voltage analog circuits (e.g., op-amps, ADCs) instead of high-voltage display or sensor bias | Select when system requires ±5V rails and shares same PCB footprint and control logic |
| MAX17504ATP+T | Single-channel synchronous step-down controller; requires external FETs, inductors, and feedback network | Designed for high-current (>1A) single-rail conversion; lacks integrated inverting capability or dual-rail coordination | Choose only if higher output current, adjustable voltage, or different topology justifies added complexity and component count |
Compared with LT3582EUD-12#PBF, LT3582EUD-5#PBF offers identical integration and reliability but targets lower-voltage applications, while MAX17504ATP+T provides greater flexibility at the cost of design effort, bill-of-materials expansion, and loss of coordinated dual-rail startup behavior.
Availability
LT3582EUD-12#PBF is available at Aetrix Electronics and suitable for AMOLED display bias, CCD sensor power, and industrial instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for LT3582EUD-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LT3582 product line was designed specifically for compact, high-efficiency dual-rail power conversion in space-constrained imaging and display systems - emphasizing integration, thermal robustness, and factory-configurable reliability.
FAQ
Is LT3582EUD-12#PBF pin-compatible with LT3582EUD-5#PBF?
Yes, LT3582EUD-12#PBF and LT3582EUD-5#PBF share identical 16-pin 3mm × 3mm QFN packaging, pin assignments, and electrical interface. The only functional difference is factory-programmed output voltage: ±12V for LT3582EUD-12#PBF versus ±5V for LT3582EUD-5#PBF. No PCB layout changes are needed when substituting between these variants.
Does LT3582EUD-12#PBF require I²C configuration to operate?
No, LT3582EUD-12#PBF does not require I²C configuration. Its OTP memory is pre-programmed at the factory for ±12V outputs, simultaneous power-up sequencing, and enabled power-down discharge. The SDA and SCL pins may be tied to GND or VIN per datasheet guidance - no microcontroller or I²C host is necessary for basic operation.
What is the maximum load current supported by LT3582EUD-12#PBF on each rail?
LT3582EUD-12#PBF supports up to 80mA on the +12V (VOUTP) rail and up to 85mA on the –12V (VOUTN) rail under typical conditions with proper thermal management. These values derive from the boost switch current limit (350mA) and inverting switch current limit (600mA), factoring in conversion efficiency, inductor DCR, and ambient temperature.
Can LT3582EUD-12#PBF be used with a 3.3V input supply?
Yes, LT3582EUD-12#PBF operates with input voltages from 2.55V to 5.5V, fully supporting 3.3V nominal supplies. At 3.3V input, it maintains regulation across its full load range for both ±12V outputs, with typical efficiency exceeding 80% at 50mA per rail - verified in the datasheet's efficiency plots and load regulation curves.
How is thermal performance managed in the LT3582EUD-12#PBF QFN package?
LT3582EUD-12#PBF uses a 16-pin 3mm × 3mm QFN with an exposed thermal pad (Pin #17) that must be soldered to a PCB ground plane. With θJA = 68°C/W, the package dissipates heat effectively - enabling continuous operation at 125°C junction temperature when layout follows Linear Technology's recommended copper pour and via guidelines for the exposed pad.
LT3582EUD-12#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive and Negative (Dual Rail)
- Topology:
- Boost, Buck-Boost
- Output Type:
- Fixed
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.55V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- ±12V
- Voltage - Output (Max):
- -
- Current - Output:
- 285mA (Switch), 490mA (Switch)
- Frequency - Switching:
- -
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (3x3)
LT3582EUD-12#PBF FAQ
1.How can I place an order for LT3582EUD-12#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3582EUD-12#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3582EUD-12#PBF reliable?
The price and inventory of LT3582EUD-12#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3582EUD-12#PBF is usually 5 days.
3.What payment methods are accepted for LT3582EUD-12#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT3582EUD-12#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3582EUD-12#PBF?
LT3582EUD-12#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3582EUD-12#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3582EUD-12#PBF?
For technical support, including LT3582EUD-12#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3582EUD-12#PBF requirements.
6.How does Aetrix verify that LT3582EUD-12#PBF is sourced from the original manufacturer or authorized distributors?
All LT3582EUD-12#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3582EUD-12#PBF meets industry standards.
7.What is the process for return or replacement of LT3582EUD-12#PBF?
All LT3582EUD-12#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3582EUD-12#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3582EUD-12#PBF part is unused and in its original packaging.
Return procedure for LT3582EUD-12#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LT3582EUD-12#PBF Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

