Analog Devices Inc. LT3640EUFD#PBF

Overview

LT3640EUFD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel monolithic buck switching regulator IC with integrated power-on reset and window-mode watchdog timer. It delivers 3.3V/0.8A from 4–35V input (HV channel) and 1.8V/0.8A from 2.5–5.5V input (LV channel), operating synchronously at 350kHz–2.5MHz. Used in automotive ECU power rails requiring fault-tolerant sequencing and microprocessor supervision.

For engineers reviewing the LT3640EUFD#PBF datasheet, LT3640EUFD#PBF pinout, LT3640EUFD#PBF application, or LT3640EUFD#PBF equivalent, key selection criteria include dual-output voltage tracking, programmable POR/watchdog timing via external capacitors, cycle-by-cycle current limiting on both channels, Burst Mode® operation for light-load efficiency, and thermal performance in the 4mm × 5mm QFN-28 package with exposed pad.

Technical Context

The LT3640EUFD#PBF integrates two independent current-mode PWM controllers sharing a single adjustable oscillator. The high-voltage nonsynchronous channel uses an internal 2.4A NPN switch with BST-driven gate drive; the low-voltage synchronous channel employs integrated PMOS/NMOS power switches with valley-current limiting and reverse-current protection.

Its power-on reset asserts RST1/RST2 until FB1 > 1.165V and FB2 > 550mV, timed by CPOR capacitor; the window-mode watchdog monitors WDI pulse edges using CWDT-set upper/lower boundaries (e.g., 2.0ms–32ms at 820pF), asserting WDO if pulses violate timing windows - enabling robust µP supervision without software intervention.

Key Specifications

Pinout & Package

The LT3640EUFD#PBF is housed in a thermally enhanced 28-pin (4mm × 5mm) plastic QFN package with exposed GND pad (Pin 29), θ_JA = 34°C/W, θ_JC = 2.7°C/W. All GND pins (15, 16, 23, 26, 29) must be soldered to PCB ground plane for thermal and noise integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output buck regulator applications.

Compared with LTC3631EUF#PBF and TPS65263-1RGER, the LT3640EUFD#PBF uniquely combines wide-input HV buck, self-contained LV synchronous buck, and hardware-based window watchdog - making it the only option for automotive-grade dual-rail systems requiring autonomous µP supervision without external ICs.

Availability

LT3640EUFD#PBF is available at Aetrix Electronics and suitable for automotive electronic control units, industrial PLC I/O modules, and medical infusion pump controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LT3640EUFD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.

The LT3640EUFD#PBF belongs to ADI's Power by Linear™ portfolio of monolithic DC/DC regulators, engineered specifically for automotive, industrial, and medical systems demanding high reliability, integrated supervision, and wide-input operation.

FAQ

What is the maximum input voltage rating for the LT3640EUFD#PBF?

The LT3640EUFD#PBF has an absolute maximum VIN rating of 55V for nonrepetitive 1-second transients. Its overvoltage lockout (OVLO) activates at 36.5V typical, disabling switching to protect internal circuitry while sustaining input up to 55V. Continuous operation is rated from 4V to 35V for the high-voltage channel.

How does the LT3640EUFD#PBF implement window-mode watchdog functionality?

The LT3640EUFD#PBF implements window-mode watchdog by monitoring falling edges on the WDI pin using two time thresholds set by the CWDT capacitor: a lower boundary (t_WDL) and upper boundary (t_WDU). If consecutive WDI pulses occur too close together (WDL) or too far apart (>t_WDU), the WDO pin is asserted. This detects both µP lockup and excessive timing jitter.

Can the LT3640EUFD#PBF operate with only the high-voltage channel enabled?

Yes, the LT3640EUFD#PBF can operate with only the high-voltage channel active. Pulling EN2 low disables the low-voltage channel independently. The HV channel remains fully functional with its own soft-start (SS1), feedback (FB1), and reset (RST1) - enabling flexible power sequencing in partial-load configurations.

What thermal considerations apply to the LT3640EUFD#PBF in the QFN package?

The LT3640EUFD#PBF in the 4mm × 5mm QFN package requires the exposed pad (Pin 29) to be soldered to a minimum 200mm² copper pour connected to GND for optimal thermal performance. With θ_JC = 2.7°C/W, this achieves junction-to-board temperatures ≤85°C at 1.2W dissipation in still air - critical for automotive under-hood applications.

Does the LT3640EUFD#PBF support external clock synchronization?

Yes, the LT3640EUFD#PBF supports external clock synchronization via the SYNC pin (Pin 4). An external 350kHz–2.5MHz logic-level clock (≥2V amplitude, ≥40ns pulse width) can synchronize both buck channels. The internal oscillator frequency must be set ≥20% below the lowest expected SYNC frequency using the RT resistor.