Analog Devices Inc. LT3640EUFD#TRPBF
- Part No.:
- LT3640EUFD#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LT3640EUFD#TRPBF.pdf
- Description:
- IC REG BUCK ADJ 1.1A/1.3A 28QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT3640EUFD#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel monolithic buck switching regulator IC with integrated power-on reset and window-mode watchdog timer. It delivers 3.3V/0.8A from 4–35V input (HV channel) and 1.8V/0.8A from 2.5–5.5V input (LV channel), operating synchronously at 350kHz–2.5MHz. Used in automotive ECU power rails requiring fault-tolerant sequencing and microprocessor supervision.
For engineers reviewing the LT3640EUFD#TRPBF datasheet, LT3640EUFD#TRPBF pinout, LT3640EUFD#TRPBF application, or LT3640EUFD#TRPBF equivalent, key selection criteria include dual-output voltage tracking, programmable reset timeout (via CPOR), windowed watchdog timing (via CWDT), and thermal performance in the 4mm × 5mm QFN-28 package with exposed pad.
Technical Context
The LT3640EUFD#TRPBF integrates two independent current-mode buck regulators sharing a single adjustable oscillator. The high-voltage channel uses a nonsynchronous NPN switch with internal 2.4A top switch and 36.5V OVLO; the low-voltage channel employs synchronous NMOS/PMOS switches with 1.1A combined current limit and 600mV FB2 reference.
Power-on reset and watchdog functions are decoupled: RST1/RST2 timers initiate after FB1 > 1.165V and FB2 > 550mV respectively, while the window-mode watchdog monitors WDI pulse spacing using CWDT-set upper/lower boundaries (e.g., 27–35ms / 1.68–2.2ms at 820pF) and asserts WDO on violation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| HV Input Range | 4V to 35V - supports wide automotive battery range; 36.5V OVLO prevents damage during load dump transients up to 55V for 1s. |
| LV Input Range | 2.5V to 5.5V - enables direct regulation from HV output or separate low-voltage rail; disables if VIN2 < 2.3V. |
| Switching Frequency | 350kHz to 2.5MHz - set by RT resistor; allows optimization of inductor size (e.g., 3.3µH at 2MHz) vs. efficiency. |
| FB1 Reference | 1.265V ±1.2% - sets HV output via resistor divider; used for RST1 assertion at 92% of this value (1.165V). |
| FB2 Reference | 600mV ±2% - sets LV output; PGOOD asserts when FB2 > 550mV with 40mV hysteresis. |
| Quiescent Current | 290µA typical - enables low-power standby mode; drops to <1µA in shutdown. |
| Thermal Resistance | θJA = 34°C/W, θJC = 2.7°C/W - exposed pad (Pin 29) must be soldered to PCB ground for effective heat dissipation. |
Pinout & Package
The LT3640EUFD#TRPBF is housed in a thermally enhanced 28-lead (4mm × 5mm) plastic QFN package with exposed GND pad (Pin 29). Package footprint complies with JEDEC MO-220, and requires soldering of the exposed pad for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (SYNC) | External clock input | Synchronizes both channels to external 350kHz–2.5MHz signal; ignores SYNC until FB1 > 1.165V. |
| Pin 2 (SS1) | HV soft-start control | Charges to ~2V internally; capacitor to GND sets ramp time for VOUT1; enables tracking when driven externally. |
| Pin 3 (FB1) | HV feedback node | Regulated to 1.265V; connects to resistor divider; RST1 released after FB1 > 1.165V. |
| Pin 4 (RT) | Oscillator frequency set | Resistor to GND programs switching frequency (e.g., 32.4kΩ → 2MHz). |
| Pin 5 (RST2) | LV power-on reset output | Open-drain; pulled low until FB2 > 550mV, then held low for CPOR-defined timeout (e.g., 9.5ms @ 220pF). |
| Pin 6 (RST1) | HV power-on reset output | Open-drain; released after FB1 > 1.165V and CPOR timeout; used for µP reset sequencing. |
| Pin 7 (WDO) | Watchdog output | Open-drain; asserted low if WDI pulses violate CWDT-set window (tWDL/tWDU); initiates reset timer on violation. |
| Pin 8 (CWDT) | Watchdog timing capacitor | Capacitor to GND sets watchdog window boundaries (e.g., 820pF → tWDU = 32ms, tWDL = 2ms). |
| Pin 9 (CPOR) | Reset timing capacitor | Capacitor to GND sets both RST1/RST2 timeout and WDO assertion duration (e.g., 220pF → 9.5ms). |
| Pin 10 (WDE) | Watchdog enable | Active-high; must be ≥0.7V to activate watchdog monitoring of WDI. |
| Pin 11 (WDI) | Watchdog input | Accepts µP pulses; falling edges trigger watchdog; min pulse width = 300ns. |
| Pins 12,13,20,23,29 (GND) | Ground terminals | Multiple GND pins + exposed pad (Pin 29) required for low-impedance return and thermal conduction. |
| Pin 15 (DA) | Catch diode anode sense | Monitors diode current for valley current limiting; critical for short-circuit protection in HV channel. |
| Pin 16 (SW1) | HV switch node | Connects to inductor and catch diode cathode; carries full HV switching current. |
| Pin 17 (SW) | Bootstrap switch node | Drives BST capacitor; internal 5mA current source charges BST during startup. |
| Pin 18 (BST) | Bootstrap supply | Provides >VIN gate drive to HV NPN switch; requires external diode and capacitor. |
| Pin 19 (VIN) | HV input supply | Primary power for IC bias and HV channel; bypass locally; absolute max 55V transient. |
| Pin 21 (VIN2) | LV input supply | Input for LV channel; powers internal circuitry when >3V; disables LV if <2.3V. |
| Pin 22 (SW2) | LV switch node | Connects to LV inductor; integrates synchronous NMOS/PMOS switches. |
| Pin 24 (EN2) | LV enable | Active-high; pulls <0.3V to disable LV channel; threshold = 1V typical. |
| Pin 25 (SS2) | LV soft-start control | Charges to ~2V internally; capacitor to GND sets VOUT2 ramp time; tracks other supplies when driven. |
| Pin 26 (FB2) | LV feedback node | Regulated to 600mV; connects to LV resistor divider; triggers PGOOD when >550mV. |
| Pin 27 (PGOOD) | Power-good indicator | Open-drain; sinks current only when FB2 is in regulation (±40mV hysteresis). |
| Pin 28 (EN/UVLO) | Global enable/UVLO | 1.26V threshold enables UVLO programming; 2µA hysteresis current prevents noise-induced shutdown. |
Key Features
| Feature | Design Value |
|---|---|
| Window-mode watchdog timer | Rejects both too-frequent and too-sparse µP pulses via independently set tWDL/tWDU boundaries-prevents false resets from software hangs or clock glitches. |
| Independent soft-start & tracking | SS1 and SS2 pins allow separate ramp control for each output or coordinated sequencing with external voltage sources. |
| Short-circuit robustness | Dual current limiting (peak + valley) per channel plus DA-sensed catch diode current ensures reliable operation under sustained overload or output short. |
| Low-ripple Burst Mode® | Maintains <10mVpp output ripple at light loads while sustaining >85% efficiency-critical for noise-sensitive analog or RF subsystems. |
| Thermally optimized QFN | 4mm × 5mm package with exposed GND pad achieves θJC = 2.7°C/W-enables 1.6A total output in compact automotive modules without forced air. |
Applications
| Automotive Engine Control Unit (ECU) | Industrial PLC I/O Module |
|---|---|
Use Scenario: Dual-rail power for MCU core (1.8V) and CAN transceiver/interface (3.3V) in under-hood ECU exposed to 12V battery transients and -40°C to 125°C ambient. IC Role / Device Role / Timing Role: Primary DC/DC regulator with integrated POR and watchdog-ensures deterministic boot sequence and detects firmware lockup during engine cranking. Use Value: Eliminates discrete reset IC and external watchdog, reducing BOM count by 2 components while guaranteeing <10ms RST1/RST2 timeout accuracy over temperature. | Use Scenario: Powering FPGA configuration logic (3.3V) and I/O banks (1.8V) in modular PLC backplane where field-replaceable modules require autonomous power sequencing. IC Role / Device Role / Timing Role: Dual-output supervisor-regulator-coordinates voltage ramp order (VOUT1 before VOUT2) and validates stable operation before enabling downstream logic. Use Value: SS1/SS2 tracking capability ensures monotonic startup across module variants; PGOOD confirms both rails before releasing FPGA DONE signal. |
| Medical Infusion Pump Controller | Test & Measurement Signal Generator |
Use Scenario: Isolated power tree for ARM-based pump controller with motor driver (3.3V) and ADC/sensor interface (1.8V), requiring fail-safe reset during brownout events. IC Role / Device Role / Timing Role: Fault-tolerant power manager-uses EN/UVLO for precise 4V brownout detection and RST1/RST2 to hold MCU in reset until both outputs stabilize. Use Value: 36.5V OVLO protects against 24V supply surges; <1µA shutdown current extends battery life during standby between infusion cycles. | Use Scenario: Low-noise dual-rail supply for high-resolution DAC (3.3V AVDD) and digital control logic (1.8V DVDD) in portable signal generators where spectral purity is critical. IC Role / Device Role / Timing Role: Precision regulator with Burst Mode®-delivers clean, low-ripple outputs without compromising light-load efficiency during idle periods. Use Value: Achieves <10mVpp output ripple at 10mA load (vs. >30mVpp in standard PWM), preserving SFDR >90dB in 16-bit DAC applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output buck regulator with supervision applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT8609S | Single-channel 42V synchronous buck with integrated MOSFETs; no LV channel or watchdog; 2.2MHz max frequency. | Lacks dual-output capability and system-level supervision-requires external reset IC and sequencer for multi-rail systems. | Select when only one regulated rail is needed and board space is constrained; not suitable as drop-in replacement. |
| TPS6521905 | Triple-output PMIC (2 buck + 1 LDO); 2.2MHz max; no programmable watchdog window; fixed 1.8V/3.3V outputs. | Fixed outputs eliminate resistor-divider design effort but prevent customization; lacks CWDT-adjustable watchdog boundaries. | Choose for cost-sensitive consumer applications where flexibility is secondary to integration density. |
Compared with LT8609S and TPS6521905, the LT3640EUFD#TRPBF uniquely combines dual independent buck regulation, programmable window watchdog, and adjustable POR in a single 4mm × 5mm QFN-enabling compact, safety-aware power designs without external supervision components.
Availability
LT3640EUFD#TRPBF is available at Aetrix Electronics and suitable for automotive electronic control units, industrial PLC modules, and medical infusion pump controllers requiring stable component supply, long-term lifecycle support, and AEC-Q200-aligned reliability.
Supply support for LT3640EUFD#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance power management ICs with rigorous automotive and industrial qualification.
The LT3640EUFD#TRPBF belongs to Linear's monolithic buck regulator product line, designed specifically for fault-tolerant, multi-rail power systems in harsh environments where integrated supervision reduces system-level complexity and improves functional safety compliance.
FAQ
What is the maximum input voltage rating for the LT3640EUFD#TRPBF?
The LT3640EUFD#TRPBF has an absolute maximum VIN rating of 55V for nonrepetitive 1-second transients. Its overvoltage lockout (OVLO) activates at 36.5V typical, disabling switching to protect internal circuitry. Continuous operation is rated up to 35V, making it suitable for 24V automotive and industrial systems with load-dump immunity.
How does the window-mode watchdog timer in the LT3640EUFD#TRPBF differ from standard watchdogs?
The LT3640EUFD#TRPBF implements a true window-mode watchdog that monitors both minimum and maximum pulse spacing on the WDI pin. Unlike simple timeout watchdogs, it asserts WDO if pulses arrive too close together (< tWDL) or too far apart (> tWDU)-detecting both software hangs and runaway loops. Boundaries are set independently via CWDT capacitor value.
Can the LT3640EUFD#TRPBF regulate both outputs simultaneously from a single 12V input?
Yes-the LT3640EUFD#TRPBF supports cascaded operation: the HV channel regulates 3.3V from 12V input, and VIN2 can be connected directly to that 3.3V output to power the LV channel for 1.8V generation. This two-stage topology is validated in the datasheet and maintains regulation as long as VIN2 stays within 2.5–5.5V and load currents remain within spec.
What thermal design considerations apply to the LT3640EUFD#TRPBF in its QFN package?
The LT3640EUFD#TRPBF QFN package requires soldering of the exposed pad (Pin 29) to a large PCB copper area tied to GND. With θJC = 2.7°C/W, proper thermal vias under the pad reduce junction-to-board resistance. For 1.6A total load at 125°C ambient, a 4cm² thermal pad with 8–12 vias (0.3mm diameter) is recommended to maintain TJ < 125°C.
Is the LT3640EUFD#TRPBF pin-compatible with other packages in the LT3640 family?
No-the LT3640EUFD#TRPBF uses the 28-pin 4mm × 5mm QFN (UFD) package, which has different pin assignments than the 28-pin TSSOP (FE) variant. Pin mapping differs significantly (e.g., FB2 is Pin 1 in UFD but Pin 26 in FE), requiring separate PCB layouts. Always verify pinout from the specific package drawing before layout.
LT3640EUFD#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 35V
- Voltage - Output (Min/Fixed):
- 0.6V, 1.265V
- Voltage - Output (Max):
- 33.97V
- Current - Output:
- 1.1A, 1.3A
- Frequency - Switching:
- 500kHz ~ 2MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-QFN (4x5)
LT3640EUFD#TRPBF FAQ
1.How can I place an order for LT3640EUFD#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3640EUFD#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3640EUFD#TRPBF reliable?
The price and inventory of LT3640EUFD#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3640EUFD#TRPBF is usually 5 days.
3.What payment methods are accepted for LT3640EUFD#TRPBF?
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Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3640EUFD#TRPBF?
LT3640EUFD#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3640EUFD#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3640EUFD#TRPBF?
For technical support, including LT3640EUFD#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3640EUFD#TRPBF requirements.
6.How does Aetrix verify that LT3640EUFD#TRPBF is sourced from the original manufacturer or authorized distributors?
All LT3640EUFD#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3640EUFD#TRPBF meets industry standards.
7.What is the process for return or replacement of LT3640EUFD#TRPBF?
All LT3640EUFD#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3640EUFD#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3640EUFD#TRPBF part is unused and in its original packaging.
Return procedure for LT3640EUFD#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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