Analog Devices Inc. LT3753EFE#PBF
- Part No.:
- LT3753EFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 38-TFSOP (0.173", 4.40mm Width) 31 Leads, Exposed Pad
- Datasheet:
-
LT3753EFE#PBF.pdf
- Description:
- IC REG CTRLR FWRD CONV 38TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:165
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LT3753EFE#PBF from Analog Devices is a current mode PWM controller optimized for active clamp synchronous forward converters, supporting 8.5V–100V input operation, programmable volt-second clamp (DVSEC), and synchronous rectification control via SOUT. It delivers high-efficiency isolated DC/DC conversion in telecom and industrial power supplies up to 400W.
For engineers reviewing the LT3753EFE#PBF datasheet, LT3753EFE#PBF pinout, LT3753EFE#PBF application, or LT3753EFE#PBF equivalent, key selection considerations include its 38-lead TSSOP package with high-voltage pin spacing, 100kHz–500kHz programmable switching frequency, active clamp timing control (tAO/tOA), and dual soft-start/stop functionality on SS1/SS2 pins.
Technical Context
The LT3753EFE#PBF implements a primary-side current-mode control architecture with integrated volt-second clamp regulation, enabling duty cycles >50% while preventing transformer saturation. Its DVSEC clamp is programmed via IVSEC and UVLO_VSEC pins using external resistors, and operates independently of opto-coupler feedback.
It features three independent gate drivers-OUT (main switch), AOUT (active clamp MOSFET), and SOUT (secondary-side synchronous rectifier)-with programmable nonoverlap delays (tAO, tAS, tOS) and adaptive blanking. Protection includes hiccup-mode overcurrent (96mV OC threshold), UVLO/OVLO with hysteresis, and thermal shutdown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 8.5V to 100V - supports wide-range industrial and telecom inputs without pre-regulation |
| Switching Frequency | 100kHz to 500kHz - programmable via RT resistor; enables optimization of magnetics size vs. efficiency |
| DVSEC Clamp Accuracy | ±4% max duty cycle error at UVLO_VSEC = 1.25V - ensures reliable transformer reset under line/load transients |
| OC Threshold | 96mV ±11.5mV - precise primary-side overcurrent detection enabling fast hiccup-mode fault response |
| Gate Driver Output Level | 11.9V high / 0.1V low at INTVCC = 12V - drives standard N-channel MOSFETs directly without level-shifting |
| Operating Temp Range | –40°C to +125°C junction - qualified for extended industrial and automotive under-hood environments |
| INTVCC Regulator | 10V ±0.6V, 32mA max - powers all internal drivers; dropout <0.6V at 10mA enables low-VIN operation |
Pinout & Package
LT3753EFE#PBF is housed in a 38-lead plastic TSSOP (FE package) with missing pins (23, 25, 27, 29, 31, 33, 35) for enhanced high-voltage creepage and reliability. The exposed pad (Pin 39) is electrically connected to PGND and GND and must be soldered to a PCB ground plane for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (28) | Main supply input | Accepts 8.5V–100V; powers internal LDO (INTVCC) and bias circuits |
| OUT (24) | Main switch gate driver | Drives N-MOSFET primary switch; 11.9V output swing, 19ns rise/fall |
| AOUT (32) | Active clamp switch driver | Controls external clamp MOSFET; programmable delay tAO relative to OUT |
| SOUT (30) | Synchronous rectifier driver | Signals secondary-side SR MOSFET; delay tSO/tOS programmable for ZVS/ZCS optimization |
| IVSEC (8) | DVSEC clamp programming | Resistor sets maximum duty cycle inversely proportional to VIN - prevents saturation |
| UVLO_VSEC (9) | Volt-second clamp reference | Resistor divider sets both UVLO threshold and DVSEC scaling; 5µA hysteresis current |
| ISENSEP (21) / ISENSEN (20) | Primary current sense inputs | Kelvin-connected to source resistor; supports slope compensation via series R |
| OC (22) | Hiccup-mode overcurrent input | 96mV threshold, duty-cycle independent - triggers fault protection without latch-up |
| SS1 (7) / SS2 (17) | Soft-start/stop control | SS1 controls frequency/DVSEC ramp-up/down; SS2 controls COMP ramp for loop stability |
| PGND (19, 38, 39) | Power ground return | Exposed pad (39) is primary thermal path; must be soldered to large copper area |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Volt-Second Clamp (DVSEC) | Enables >50% duty cycles while guaranteeing transformer reset - eliminates need for auxiliary winding or opto-coupler in open-loop regulation |
| Three Independent Gate Drivers | OUT/AOUT/SOUT with nanosecond-level timing control (tAO, tAS, tOS) - allows precise dead-time tuning for ZVS in active clamp topology |
| Adaptive Leading Edge Blanking + Extended Blanking | Configurable via TBLNK resistor - suppresses false triggering during MOSFET turn-on dV/dt spikes |
| Programmable UVLO/OVLO with Hysteresis | UVLO_VSEC and OVLO pins accept resistor dividers - provides robust input voltage supervision with user-defined thresholds and hysteresis |
| Dual Soft-Start/Stop Architecture | SS1 controls frequency and DVSEC; SS2 controls COMP - enables controlled startup/shutdown of both power stage and control loop |
| Micropower Shutdown Mode | VIN quiescent current drops to 20–40µA when UVLO_VSEC < 0.4V - ideal for standby power-sensitive systems |
Applications
| 48V Telecom Isolated PSU | Industrial 24/48V Input Power |
|---|---|
|
Use Scenario: 36V–72V input, 5V/20A isolated forward converter for base station RF power amplifiers. IC Role / Device Role / Timing Role: Primary-side controller managing active clamp reset, synchronous rectification timing, and volt-second clamping to maintain regulation across wide input range. Use Value: Enables >92% efficiency at full load and stable output under rapid 50% load steps without secondary-side feedback components. |
Use Scenario: DIN-rail mounted 400W industrial power supply with 24V/48V nominal input and 12V/24V outputs. IC Role / Device Role / Timing Role: Core PWM controller implementing active clamp forward topology with programmable fault thresholds and thermal derating. Use Value: Supports extended temperature operation (–40°C to +125°C) and meets EN 62368-1 reinforced isolation requirements via high-voltage pin spacing. |
| Automotive 48V Mild Hybrid Systems | Military Vehicle DC/DC Conversion |
|
Use Scenario: 24V–60V battery-supplied DC/DC converter powering infotainment and ADAS subsystems in 48V architectures. IC Role / Device Role / Timing Role: Active clamp forward controller providing regulated 5V/3.3V rails with hiccup-mode OCP and programmable soft-stop for safe shutdown during battery disconnect. Use Value: Eliminates transformer saturation risk during cold-crank events (VIN dip to 6V) via DVSEC clamp and UVLO hysteresis. |
Use Scenario: Ruggedized 28V–110V input power module for airborne avionics requiring MIL-STD-704 compliance. IC Role / Device Role / Timing Role: High-reliability forward controller with missing-pin TSSOP package, extended temp grade (–55°C to +150°C MP variant), and radiation-tolerant design practices. Use Value: Delivers 400W output with single-chip solution, reducing BOM count and improving mean time between failures (MTBF). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar active clamp forward controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT3752-1HFE#PBF | High-side active clamp topology; different pinout and timing logic; no SOUT output | Requires high-side clamp MOSFET placement; not suitable for secondary-side synchronous rectification | Select only when high-side clamp configuration is mandated by layout or EMI constraints |
| UCC2897APWR | Fixed 50% max duty cycle; no volt-second clamp; requires opto-coupler for regulation; SOIC-16 package | Lacks DVSEC open-loop regulation capability; limited to lower-power designs (<150W) | Choose only for cost-sensitive, lower-power applications where transformer reset is managed externally |
Compared with LT3752-1HFE#PBF and UCC2897APWR, the LT3753EFE#PBF uniquely integrates programmable DVSEC clamp, SOUT-driven synchronous rectification, and 38-pin TSSOP packaging with HV spacing - making it the only option for high-efficiency, high-power (>200W), opto-free active clamp forward designs requiring secondary-side SR control.
Availability
LT3753EFE#PBF is available at Aetrix Electronics and suitable for 48V telecom isolated PSUs, industrial 24/48V input power modules, and automotive 48V mild hybrid systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LT3753EFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and aerospace markets.
The LT3753EFE#PBF belongs to Analog Devices' Power by Linear™ active clamp controller product line, designed specifically for high-efficiency, high-voltage isolated DC/DC conversion in telecom, industrial, and military applications.
FAQ
What is the maximum operating junction temperature for the LT3753EFE#PBF?
The LT3753EFE#PBF is rated for –40°C to +125°C junction temperature. This grade is verified per Analog Devices' characterization and statistical process controls. Derating curves and thermal resistance data (θJA = 25°C/W) are provided in the datasheet to support PCB thermal design for continuous 400W operation.
How does the DVSEC volt-second clamp function in the LT3753EFE#PBF?
The DVSEC clamp in the LT3753EFE#PBF uses UVLO_VSEC and IVSEC pins to program a maximum duty cycle inversely proportional to system input voltage. At UVLO_VSEC = 1.25V and RIVSEC = 51.1kΩ, it delivers 72.5% max duty cycle - preventing transformer saturation during line dips or load surges without requiring secondary feedback.
Can the LT3753EFE#PBF drive synchronous rectifiers on the secondary side?
Yes, the LT3753EFE#PBF provides dedicated SOUT output with programmable timing (tSO, tOS) to control external N-channel MOSFETs on the secondary side. This enables high-efficiency synchronous rectification in forward topologies, replacing Schottky diodes and reducing conduction losses by >30% at 20A output.
What are the key timing parameters controlled by TAO, TAS, and TOS pins on the LT3753EFE#PBF?
TAO sets delay from AOUT rise to OUT rise (tAO); TAS sets delay from SOUT fall to OUT rise (tAS); TOS sets delay from OUT fall to SOUT rise (tOS). These resistors enable precise nonoverlap control - critical for zero-voltage switching in active clamp forward converters and avoiding shoot-through in synchronous rectifiers.
Does the LT3753EFE#PBF support synchronization to an external clock?
Yes, the LT3753EFE#PBF supports external clock synchronization via the SYNC pin. It accepts TTL/CMOS-compatible signals from 100kHz to 500kHz with 1.2V–1.8V high threshold and 0.6V–1.025V low threshold. Frequency tracking accuracy is ±25% of programmed fOSC, enabling multi-phase or noise-spread clocking in dense power systems.
LT3753EFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 38-TFSOP (0.173", 4.40mm Width) 31 Leads, Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Positive, Isolation Capable
- Topology:
- Forward Converter
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 8.5V ~ 100V
- Frequency - Switching:
- 100kHz ~ 500kHz
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Frequency Control, Soft Start
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-TSSOP-EP
LT3753EFE#PBF FAQ
1.How can I place an order for LT3753EFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3753EFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3753EFE#PBF reliable?
The price and inventory of LT3753EFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3753EFE#PBF is usually 5 days.
3.What payment methods are accepted for LT3753EFE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT3753EFE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3753EFE#PBF?
LT3753EFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3753EFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3753EFE#PBF?
For technical support, including LT3753EFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3753EFE#PBF requirements.
6.How does Aetrix verify that LT3753EFE#PBF is sourced from the original manufacturer or authorized distributors?
All LT3753EFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3753EFE#PBF meets industry standards.
7.What is the process for return or replacement of LT3753EFE#PBF?
All LT3753EFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3753EFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3753EFE#PBF part is unused and in its original packaging.
Return procedure for LT3753EFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LT3753EFE#PBF Tags

-
UCC28C45DR
Texas Instruments

-
UCC28C40DR
Texas Instruments

-
UCC28C43DR
Texas Instruments

-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments

-
MIC2102YML-TR
Microchip Technology

-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments

-
LM5155DSSR
Texas Instruments

-
LM25085MYX/NOPB
Texas Instruments

-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

