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Analog Devices Inc. LT3837EFE#PBF
- Part No.:
- LT3837EFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LT3837EFE#PBF.pdf
- Description:
- IC REG CTRLR FLYBACK 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:631
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Product details
Overview
LT3837EFE#PBF from Analog Devices (formerly Linear Technology) is an isolated no-opto synchronous flyback controller IC designed for medium-power DC-DC conversion in 10W–60W isolated supplies. It regulates output voltage by sensing secondary-side flyback voltage via a transformer auxiliary winding, eliminating optocouplers. Key confirmed parameters: 4.5V–20V VCC input range, 50kHz–250kHz programmable switching frequency, 1.237V feedback reference voltage, 98mV current-sense threshold, and operation in forced continuous conduction mode. It drives primary-side and synchronous secondary-side MOSFETs in isolated flyback topologies.
For engineers reviewing the LT3837EFE#PBF datasheet, LT3837EFE#PBF pinout, LT3837EFE#PBF application, or LT3837EFE#PBF equivalent, this page delivers verified technical context-including isolated feedback timing behavior, load compensation implementation, synchronous gate drive timing constraints, and thermal design guidance for the 16-pin TSSOP package with exposed pad-enabling accurate system-level validation and BOM selection.
Technical Context
The LT3837EFE#PBF implements a current-mode control architecture with a unique flyback feedback amplifier that samples transformer auxiliary winding voltage only during the flyback period, enabling precise regulation without optoisolators. Its internal collapse-detect comparator disables the feedback amplifier when the sensed voltage drops below 80% of VFB, ensuring stable loop dynamics.
It integrates dedicated timing functions including programmable minimum on-time (tON), enable delay (ENDLY), and PG-to-SG delay (PGDLY), all set via external resistors. The controller operates in forced continuous conduction mode to improve cross-regulation in multi-output designs and supports external synchronization via the SYNC pin with 1.53V threshold and 40kΩ input resistance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Operating Range | 4.5V to 20V - powers internal circuitry and gate drivers; supports wide-input industrial and telecom supplies. |
| Feedback Reference Voltage (VFB) | 1.237V (typ) - sets output voltage accuracy; used with external resistor divider to define regulated output. |
| Switching Frequency Range | 50kHz to 250kHz - user-programmable via OSC capacitor; enables optimization of size, efficiency, and EMI. |
| Current Sense Threshold | 98mV (typ) at SENSE+–SENSE− - determines peak primary current limit; directly scales with external sense resistor. |
| UVLO Threshold | 1.240V (typ) - disables gate outputs when VIN-derived UVLO pin falls below threshold; provides input undervoltage protection. |
| Soft-Start Charging Current | 20µA (typ) - controls ramp rate of SFST pin voltage; limits inrush current during startup. |
| Gate Drive Outputs | PG/SG high level ≥7.4V, low level ≤0.05V - drives N-channel MOSFETs directly; supports logic-level and standard-threshold devices. |
| Thermal Rating | Junction temperature range –40°C to 125°C - validated for industrial and medical environments; requires exposed pad soldering for thermal performance. |
Pinout & Package
The LT3837EFE#PBF is housed in a thermally enhanced 16-lead plastic TSSOP package (FE package) with exposed pad (Pin 17) that must be soldered to PCB ground for electrical integrity and thermal dissipation (θJA = 40°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SG (1) | Synchronous gate drive output | Drives secondary-side MOSFET; high-current output with 15ns rise time into 1nF load. |
| VCC (2) | Supply voltage input | Power rail for internal circuitry and gate drivers; requires ≥4.7µF bypass capacitor to GND. |
| tON (3) | Minimum on-time programming | Resistor sets absolute minimum primary switch conduction time per cycle to ensure flyback sampling. |
| ENDLY (4) | Enable delay programming | Resistor sets fixed delay after primary switch turn-off before feedback amplifier activation; rejects leakage inductance spike. |
| SYNC (5) | External clock synchronization input | Accepts external clock edges to align oscillator; 1.53V threshold; tie to GND if unused. |
| SFST (6) | Soft-start control | Capacitor-to-GND sets VC ramp-up time (~70ms/µF); prevents inrush current at startup. |
| OSC (7) | Oscillator timing | Capacitor-to-GND sets switching frequency (fOSC ≈ 100kHz × 100/COSC(pF)). |
| FB (8) | Feedback amplifier input | Receives scaled flyback voltage; high-gain transconductance amplifier (1000µmho typ) referenced to 1.237V. |
| VC (9) | Control voltage output | Integrates feedback error current; sets peak current limit; connects to compensation network. |
| UVLO (10) | Input undervoltage lockout | Resistive divider from VIN sets shutdown threshold; includes hysteresis controlled by divider impedance. |
| SENSE– (11), SENSE+ (12) | Primary current sense inputs | Differential pair measures voltage across external sense resistor; blanked during tON(MIN) period. |
| CCMP (13) | Load compensation filter | Connects 0.1µF ceramic capacitor to GND; filters average primary current signal for load compensation. |
| RCMP (14) | Load compensation resistor | Adjusts compensation gain; cancels output impedance error (ESR + RDS(ON)) in high-accuracy applications. |
| PGDLY (15) | PG-to-SG delay programming | Resistor sets delay from SG turn-off to PG turn-on; ensures safe dead-time in synchronous operation. |
| PG (16) | Primary gate drive output | Drives primary-side MOSFET; high-current output with 11ns rise time into 1nF load. |
| GND (17) | Signal and power ground | Exposed pad; must be soldered to PCB ground plane for thermal management and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| No-opto isolated regulation | Uses transformer auxiliary winding voltage during flyback period-eliminates optocoupler, improves dynamic response and long-term reliability. |
| Synchronous rectification support | Dual gate drivers (PG/SG) with matched timing and fast edge rates (≤15ns) enable high-efficiency secondary-side synchronous MOSFET control. |
| Programmable timing functions | Independent resistor-programmable tON, ENDLY, PGDLY, and soft-start allow precise control of flyback sampling window and startup behavior. |
| Load compensation | RCMP/CCMP interface actively corrects for output impedance errors (ESR + RDS(ON)) to maintain tight regulation across load range. |
| Forced continuous conduction mode | Ensures consistent coupling between multiple secondary windings-critical for cross-regulation in multi-output isolated supplies. |
| Robust protection suite | Includes undervoltage lockout (UVLO), overcurrent fault detection (230mV sense fault threshold), and thermal shutdown. |
Applications
| Medical Isolated Power | Industrial Instrumentation Supply |
|---|---|
Use Scenario: 3.3V/10A isolated DC-DC converter powering patient-connected monitoring circuits in Class II medical equipment. IC Role / Device Role / Timing Role: LT3837EFE#PBF serves as primary-side controller, sampling flyback voltage from auxiliary winding to regulate output without optocoupler; manages PG/SG timing to ensure safe synchronous rectification. Use Value: Meets IEC 60601 creepage/clearance requirements via transformer isolation while achieving >88% efficiency at full load and ±1.5% output regulation across line/load/temperature. | Use Scenario: 9V–18V input to 3.3V isolated supply for precision analog front-ends in factory automation sensors. IC Role / Device Role / Timing Role: LT3837EFE#PBF implements isolated feedback with load compensation (RCMP/CCMP) to cancel IR drops across secondary traces and MOSFET RDS(ON), maintaining <±0.5% regulation at 10A. Use Value: Enables stable 16-bit ADC reference performance under varying load conditions without optocoupler aging or CMTI limitations. |
| Telecom DC-DC Module | Test Equipment Auxiliary Supply |
Use Scenario: Compact 48V input to 5V/6A isolated flyback in telecom shelf power modules requiring high power density and low EMI. IC Role / Device Role / Timing Role: LT3837EFE#PBF operates in forced CCM with externally synchronized switching (via SYNC pin) to reduce beat frequencies and meet CISPR-32 conducted emissions limits. Use Value: Achieves 86% efficiency at 100kHz with minimal output ripple (<20mVpp) and eliminates optocoupler-related failure modes in field-deployed systems. | Use Scenario: Bench-top test instrument requiring dual isolated 12V/1A and 5V/2A outputs from single 24V input. IC Role / Device Role / Timing Role: LT3837EFE#PBF controls multi-winding transformer with forced CCM and precise ENDLY/tON tuning to achieve <±2% cross-regulation between outputs. Use Value: Delivers stable, low-noise rails for sensitive DUT interfaces without separate regulators or optocoupler trimming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated flyback controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28911DR | Primary-side sensing with integrated high-voltage FET; no external PG/SG drivers; fixed 70kHz frequency; no load compensation or programmable timing. | Targeted at lower-cost, lower-power (<10W) AC/DC adapters; lacks synchronous drive and multi-output cross-regulation features. | Select UCC28911DR only for cost-sensitive, single-output, sub-10W applications where synchronous rectification and precision load regulation are not required. |
| MAX17690ATP+ | Integrated dual gate drivers (high/low side), but designed for active clamp forward-not flyback; requires optocoupler for isolation; no no-opto flyback feedback architecture. | Optimized for higher-efficiency active clamp forward topologies in 30W–100W range; incompatible with transformer-based no-opto flyback implementation. | Choose MAX17690ATP+ only for active clamp forward designs; not a functional substitute for LT3837EFE#PBF's isolated no-opto flyback control. |
Compared with UCC28911DR and MAX17690ATP+, the LT3837EFE#PBF uniquely combines no-opto isolated regulation, dual synchronous gate drive, programmable timing, and load compensation-making it the only viable option for high-accuracy, medium-power, multi-output isolated flyback supplies requiring long-term reliability and design flexibility.
Availability
LT3837EFE#PBF is available at Aetrix Electronics and suitable for medical isolated power, industrial instrumentation supplies, and telecom DC-DC modules requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.
Supply support for LT3837EFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, formed through the acquisition of Linear Technology in 2017.
The LT3837EFE#PBF belongs to ADI's isolated power controller product line, engineered specifically for high-reliability, medium-power isolated flyback converters where optocoupler elimination, synchronous rectification, and tight cross-regulation are critical design requirements.
FAQ
What is the function of the ENDLY pin on the LT3837EFE#PBF?
The ENDLY pin on the LT3837EFE#PBF programs a fixed enable delay time-typically 265ns-between primary MOSFET turn-off and activation of the flyback feedback amplifier. This delay allows transformer leakage inductance spikes to settle before sampling the flyback voltage, preventing regulation errors. It is set using an external resistor to ground, and its value is confirmed in the Electrical Characteristics table (tED = 265ns, typical). The LT3837EFE#PBF relies on this timing to maintain accuracy in isolated no-opto operation.
Can the LT3837EFE#PBF operate without an external soft-start capacitor?
Yes, the LT3837EFE#PBF can operate without an external soft-start capacitor: the SFST pin may be left open to disable soft-start functionality. However, doing so removes inrush current limiting, which may cause excessive stress on input capacitors and MOSFETs during startup. When enabled, the SFST pin's 20µA (typ) charging current ramps VC voltage over ~70ms per µF of capacitance. For reliable operation in production systems, Analog Devices recommends using a soft-start capacitor-especially in high-current applications like the 3.3V/10A reference design shown in the LT3837EFE#PBF datasheet.
How does load compensation work on the LT3837EFE#PBF?
Load compensation on the LT3837EFE#PBF uses the RCMP and CCMP pins to inject a correction current into the FB node proportional to average primary current, thereby offsetting voltage drop errors caused by secondary-side ESR and MOSFET RDS(ON). A 0.1µF capacitor on CCMP filters the internal 50kΩ current-sense signal, and RCMP sets the gain. This function is optional: RCMP may be left open and CCMP shorted to GND in less demanding applications. The LT3837EFE#PBF datasheet provides the full derivation and design equations for calculating RCMP based on transformer turns ratio and expected output impedance.
What is the maximum duty cycle supported by the LT3837EFE#PBF?
The LT3837EFE#PBF supports a maximum switch duty cycle of 88% (typical), as specified in the Electrical Characteristics table under "Maximum Switch Duty Cycle." This limit ensures proper timing margin for flyback sampling, enable delay, and collapse detection within each switching cycle. Exceeding this duty cycle risks incomplete flyback sampling or feedback amplifier disable timing violations. The controller achieves this in forced continuous conduction mode, which improves cross-regulation in multi-output designs-confirmed in the LT3837EFE#PBF Typical Application schematic and efficiency curves.
Is the exposed pad (Pin 17) of the LT3837EFE#PBF electrically connected to ground?
Yes, the exposed pad (Pin 17) of the LT3837EFE#PBF is internally connected to signal and gate driver ground (GND), and must be soldered to the PCB ground plane. This connection is mandatory for both electrical functionality and thermal performance: the datasheet specifies θJA = 40°C/W and θJC = 10°C/W, contingent on proper pad soldering. Failure to connect the exposed pad results in degraded thermal dissipation, potential junction temperature exceedance, and unstable gate drive behavior. The LT3837EFE#PBF's thermal design guidelines explicitly require this mechanical and electrical bond.
LT3837EFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Positive, Isolation Capable
- Topology:
- Flyback
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 20V
- Frequency - Switching:
- 100kHz
- Duty Cycle (Max):
- 88%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Enable, Frequency Control, On Time Control
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP-EP
LT3837EFE#PBF FAQ
1.How can I place an order for LT3837EFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT3837EFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT3837EFE#PBF reliable?
The price and inventory of LT3837EFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT3837EFE#PBF is usually 5 days.
3.What payment methods are accepted for LT3837EFE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT3837EFE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT3837EFE#PBF?
LT3837EFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT3837EFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT3837EFE#PBF?
For technical support, including LT3837EFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT3837EFE#PBF requirements.
6.How does Aetrix verify that LT3837EFE#PBF is sourced from the original manufacturer or authorized distributors?
All LT3837EFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT3837EFE#PBF meets industry standards.
7.What is the process for return or replacement of LT3837EFE#PBF?
All LT3837EFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT3837EFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT3837EFE#PBF part is unused and in its original packaging.
Return procedure for LT3837EFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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