Analog Devices Inc. LT6119IMS-2#PBF

Overview

LT6119IMS-2#PBF from Analog Devices (formerly Linear Technology) is a high-side current sense amplifier with integrated 400mV precision reference and two same-polarity latching comparators, designed for overcurrent/undercurrent fault detection in industrial and automotive power systems. It delivers 200µV max input offset, 0.2% max gain error, 1MHz bandwidth, and operates from 2.7V to 60V supply across –40°C to 85°C.

For engineers reviewing the LT6119IMS-2#PBF datasheet, LT6119IMS-2#PBF pinout, LT6119IMS-2#PBF application, or LT6119IMS-2#PBF equivalent, this device supports fast-response motor control protection, battery monitoring with early-warning thresholds, and high-voltage industrial shunt measurement where latch-enabled comparator polarity alignment is required.

Technical Context

The LT6119IMS-2#PBF implements a current-output sense amplifier architecture that forces SENSEHI to match SENSELO potential, generating IOUTA = VSENSE / RIN. Its dual comparators share the same internal 400mV reference and identical inverting polarity (INC1 and INC2 both referenced to VREF), enabling synchronized overcurrent flagging.

Propagation delay is 1.4µs typical with 500ns step response; comparator hysteresis is 3–15mV; and latch enable/disable is controlled via the LE pin, which also supports power-on reset. The device maintains ±1.25% total threshold error and 110dB min CMRR at 60V common-mode voltage.

Key Specifications

Pinout & Package

LT6119IMS-2#PBF is housed in a 10-lead MSOP package (θJA = 160°C/W), optimized for high-voltage PCB layout with isolated sense pins and open-drain outputs rated to 60V above V–.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-side current sense amplifier applications.

Compared with MAX40056ASA+T and INA302A3QDGKRQ1, the LT6119IMS-2#PBF offers unique same-polarity dual latching comparators with integrated reference and user-configurable gain-enabling compact, high-reliability overcurrent architectures without external components or compromise on timing or voltage range.

Availability

LT6119IMS-2#PBF is available at Aetrix Electronics and suitable for industrial motor control, battery management systems, and automotive load monitoring requiring stable component supply across extended temperature ranges and high-voltage operation.

Supply support for LT6119IMS-2#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its legacy high-performance analog portfolio, emphasizing precision signal conditioning, power management, and high-reliability interface ICs for demanding applications.

The LT6119 product line was developed to address high-side current sensing challenges in industrial and automotive systems where accuracy, speed, and integration of reference/comparators reduce system complexity and improve fault response fidelity.

FAQ

What is the key functional difference between LT6119IMS-2#PBF and LT6119IMS-1#PBF?

The LT6119IMS-2#PBF features two comparators with the same polarity (both inverting inputs referenced to the 400mV internal reference), whereas the LT6119IMS-1#PBF uses opposing polarity (one inverting, one non-inverting). This makes the LT6119IMS-2#PBF ideal for dual overcurrent flags or cascaded fault responses, while LT6119IMS-1#PBF supports windowed current detection. Both share identical amplifier specs, pinout, and package.

Can LT6119IMS-2#PBF operate with a 3.3V logic interface for its comparator outputs?

Yes - the OUTC1 and OUTC2 pins are open-drain outputs rated to 60V above V–, so they can be pulled up to 3.3V (or any voltage ≤60V above V–) with an external resistor. When tripped, they sink current to V–; when inactive, they float, allowing clean interfacing with 3.3V microcontrollers or FPGAs without level shifters. The LT6119IMS-2#PBF's VOL is 220mV max at 500µA sink current.

How is gain configured on LT6119IMS-2#PBF, and what is the recommended RIN range?

Gain is set externally via RIN between V+ and SENSEHI: IOUTA = VSENSE / RIN. VOUT is then generated by ROUT from OUTA to V–: VOUT = IOUTA × ROUT. Recommended RIN is 100Ω–1kΩ; lower values increase speed but raise IOUTA (max 1mA), while higher values improve stability but reduce bandwidth. For 100× gain, use RIN = 100Ω and ROUT = 10kΩ per datasheet Table 1.

Does LT6119IMS-2#PBF support Kelvin (4-wire) shunt connections, and why is this important?

Yes - the separate SENSEHI and SENSELO pins are explicitly designed for Kelvin connection to opposite ends of the shunt resistor. This eliminates errors from PCB trace resistance and solder joint voltage drops, especially critical at high currents (e.g., 10A through 1mΩ trace adds 10mV error). The LT6119IMS-2#PBF's 200µV offset means even 1mV layout error degrades dynamic range by >5× - making Kelvin routing essential for accuracy.

What is the role of the LE pin on LT6119IMS-2#PBF, and how does it affect comparator behavior?

The LE (Latch Enable) pin controls comparator latching: when high, OUTC1/OUTC2 latch low upon threshold crossing and remain latched until LE goes low or power is cycled; when low, comparators operate transparently (output follows input). LE also initiates power-on reset, clearing latches at startup. This allows flexible fault capture strategies - e.g., LE pulsed after MCU reads flags to reset for next event - without requiring external SR latches.