Analog Devices Inc. LT6372HUDC-0.2#PBF

Overview

LT6372HUDC-0.2#PBF from Analog Devices is a precision funneling instrumentation amplifier with integrated output clamping and level-shift capability, designed for high-accuracy signal conditioning in data acquisition systems. It delivers 60µV max input offset voltage, 80dB min DC CMRR at G = 0.2, 4MHz –3dB bandwidth (G = 0.2), and operates from ±2.375V to ±17.5V supplies across –40°C to 125°C. It enables ±10V bridge or thermocouple inputs to be safely funneled and level-shifted into a 5V ADC input range.

For engineers reviewing the LT6372HUDC-0.2#PBF datasheet, LT6372HUDC-0.2#PBF pinout, LT6372HUDC-0.2#PBF application, or LT6372HUDC-0.2#PBF equivalent, this device is selected when sub-100µV offset, <35ppm/°C gain drift, integrated RFI filtering, output clamping, and split-reference level shifting are required for industrial sensor interfaces interfacing to SAR or delta-sigma ADCs.

Technical Context

The LT6372HUDC-0.2#PBF implements an enhanced three-op-amp instrumentation topology with laser-trimmed resistors (R1/R2 = 12.1kΩ) enabling single-resistor gain programming from G = 0.2 to >200. Its proprietary bipolar process ensures low input bias current (±0.8nA max over –40°C to 125°C) and exceptional long-term stability.

It features a split-reference difference amplifier stage that allows independent REF1/REF2 configuration for precise output centering, plus dedicated CLHI/CLLO pins to clamp output voltage within defined limits (e.g., VCLLO + 0.45V to VCLHI – 0.45V). Integrated EMI filters on both inputs maintain DC and AC accuracy under RF interference.

Key Specifications

Pinout & Package

LT6372HUDC-0.2#PBF is housed in a 20-lead 3mm × 4mm plastic QFN package (UDC) with exposed pad connected to V– (Pin 7). The package supports high thermal performance (θ_JA = 52°C/W) and compact PCB layouts for space-constrained instrumentation modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar instrumentation amplifier applications.

Compared with AD8421ARMZ and INA826AIDRCT, the LT6372HUDC-0.2#PBF uniquely integrates clamping, level-shifting, and RFI filtering in a single H-grade QFN, reducing BOM count by up to 9 components per channel while guaranteeing sub-100µV offset over –40°C to 125°C.

Availability

LT6372HUDC-0.2#PBF is available at Aetrix Electronics and suitable for industrial data acquisition, medical sensor interfaces, and automotive test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LT6372HUDC-0.2#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LT6372 family was designed specifically for high-precision, low-drift sensor signal conditioning in harsh electromagnetic environments-emphasizing DC accuracy, integrated protection, and simplified ADC interface design.

FAQ

What is the maximum guaranteed gain error for LT6372HUDC-0.2#PBF at G = 0.2?

The LT6372HUDC-0.2#PBF has a maximum guaranteed gain error of 0.012% at G = 0.2 over the –40°C to 125°C temperature range. This specification is tested and guaranteed per Analog Devices' production test flow, ensuring predictable performance in uncalibrated industrial sensor nodes without trimming.

Does LT6372HUDC-0.2#PBF support single-supply operation?

Yes, the LT6372HUDC-0.2#PBF supports true single-supply operation from 4.75V to 35V total supply. When operated with V+ = 5V and V– = 0V, its input common-mode range extends from 1.8V to 3.6V and output swing reaches 0.5V to 4.5V (RL = 10kΩ), enabling direct interfacing to 5V ADCs without level-shifting circuitry.

How does the CLHI and CLLO functionality protect downstream ADCs in LT6372HUDC-0.2#PBF?

In the LT6372HUDC-0.2#PBF, the CLHI and CLLO pins define hard output voltage limits: the OUTPUT pin is clamped to approximately V_CLHI + 0.45V (max) and V_CLLO – 0.74V (min). This prevents overvoltage stress on ADC input ESD structures during sensor fault conditions, eliminating need for external Schottky clamps or series resistors.

What is the purpose of the dual RG terminals (+RG,F/+RG,S and –RG,F/–RG,S) on LT6372HUDC-0.2#PBF?

The LT6372HUDC-0.2#PBF uses separate "force" and "sense" terminals for each end of the external gain-setting resistor RG to eliminate errors from PCB trace resistance and solder joint variations. Routing +RG,F and +RG,S to opposite ends of RG ensures accurate gain setting even with 100mΩ parasitic resistances - critical for maintaining <0.02% gain accuracy at G = 200.

Can LT6372HUDC-0.2#PBF be used with a 3.3V ADC reference without external level-shifting?

Yes. By configuring REF1 = 0V and REF2 = 3.3V, the LT6372HUDC-0.2#PBF centers its output precisely across 0V–3.3V - matching the full-scale range of a 3.3V ADC. This split-reference architecture eliminates external op-amps or resistor dividers, preserving DC accuracy and reducing layout complexity.