Analog Devices Inc. LT6372IUDC-0.2#PBF

Overview

LT6372IUDC-0.2#PBF from Analog Devices is a precision funneling instrumentation amplifier with integrated output clamping and level-shift capability, designed for high-accuracy signal conditioning in data acquisition systems. It delivers 60µV max input offset voltage, 80dB min DC CMRR at G = 0.2, 4MHz –3dB bandwidth (G = 0.2), and operates from ±2.375V to ±17.5V supplies across –40°C to 85°C. It enables ±10V bridge sensor outputs to be safely funneled and level-shifted into a 5V ADC input range.

For engineers reviewing the LT6372IUDC-0.2#PBF datasheet, LT6372IUDC-0.2#PBF pinout, LT6372IUDC-0.2#PBF application, or LT6372IUDC-0.2#PBF equivalent, key selection considerations include guaranteed gain drift ≤35ppm/°C (G > 0.2), integrated RFI filtering on inputs, split-reference level-shifting architecture, and dual clamp pin control (CLLO/CLHI) for ADC input protection.

Technical Context

The LT6372IUDC-0.2#PBF implements an enhanced three-op-amp instrumentation topology with laser-trimmed resistors (R1/R2 = 12.1kΩ absolute) and matched bipolar input transistors (Q1/Q2) to achieve ultra-low offset drift (±0.6µV/°C) and long-term stability. Its preamp stage transconductance scales with external gain resistor RG, enabling self-adjusting bandwidth that maintains 4MHz at G = 0.2 while preserving noise performance.

It features a split-reference difference amplifier stage that allows independent REF1/REF2 configuration for precise output centering, plus dedicated CLLO and CLHI terminals that actively limit output swing to defined voltage rails-critical for protecting downstream ADCs from overvoltage. EMI filtering is monolithically integrated on both inputs.

Key Specifications

Pinout & Package

LT6372IUDC-0.2#PBF is housed in a 20-lead 3mm × 4mm plastic QFN package (UDC) with exposed pad connected to V– (Pin 7). The package supports high thermal dissipation (θ_JA = 52°C/W) and compact PCB layout for space-constrained instrumentation modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar instrumentation amplifier applications.

Compared with AD8421ARMZ and INA828IDRCT, the LT6372IUDC-0.2#PBF uniquely integrates output clamping and split-reference level shifting in a single 20-pin QFN, eliminating four to six external components while guaranteeing sub-µV/°C drift and RFI-hardened inputs for demanding industrial and medical signal chains.

Availability

LT6372IUDC-0.2#PBF is available at Aetrix Electronics and suitable for bridge amplifier designs, precision data acquisition systems, thermocouple interfaces, and medical biopotential monitoring requiring stable component supply across extended temperature ranges.

Supply support for LT6372IUDC-0.2#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LT6372 family was engineered specifically for high-accuracy, low-drift sensor signal conditioning-emphasizing DC precision, integrated protection, and simplified ADC interfacing in harsh electromagnetic environments.

FAQ

What is the maximum guaranteed gain drift for LT6372IUDC-0.2#PBF over temperature?

The LT6372IUDC-0.2#PBF guarantees gain drift ≤35ppm/°C for gains greater than 0.2, measured across the –40°C to 85°C operating range. This specification is verified using high-speed automated testing and applies to the LT6372IUDC-0.2#PBF device in its 20-pin QFN package. Gain drift at G = 0.2 is separately specified at ≤20ppm/°C.

Can LT6372IUDC-0.2#PBF interface directly with a 5V single-supply ADC?

Yes. The LT6372IUDC-0.2#PBF supports split-reference level shifting: setting REF1 = 0V and REF2 = 5V centers the output at 2.5V, while CLLO and CLHI pins can be set to 0V and 5V to clamp output between ~0.5V and ~4.5V-ensuring safe, rail-compatible drive into a 5V ADC. The LT6372IUDC-0.2#PBF requires dual supplies (e.g., ±15V) but delivers a fully referenced single-ended output.

What is the purpose of the four gain-resistor pins (+RG,F, +RG,S, –RG,F, –RG,S) on LT6372IUDC-0.2#PBF?

These four pins minimize PCB trace resistance errors when connecting the external gain-setting resistor RG. +RG,F/+RG,S and –RG,F/–RG,S must be routed separately to opposite ends of RG to avoid introducing gain error from copper resistance-especially critical at high gains (>100) where RG values drop below 100Ω. This architecture ensures <0.012% gain error at G = 0.2 in the LT6372IUDC-0.2#PBF.

Does LT6372IUDC-0.2#PBF include built-in EMI protection?

Yes. The LT6372IUDC-0.2#PBF integrates monolithic RFI filters on both +IN and –IN inputs, maintaining DC precision and AC CMRR in the presence of strong RF fields (e.g., GSM, WiFi, switch-mode power supply noise). This eliminates the need for external RC filters or ferrite beads in most industrial and medical applications, as confirmed in the LT6372-0.2 datasheet Figure 34–35.

What is the function of the exposed pad on the LT6372IUDC-0.2#PBF QFN package?

The exposed pad on the LT6372IUDC-0.2#PBF's 20-pin 3mm × 4mm QFN is internally connected to V– (Pin 7) and must be soldered to a PCB ground plane or V– copper pour. This connection lowers thermal resistance (θ_JA = 52°C/W), improves power supply rejection ratio (PSRR), and enhances stability-per Analog Devices' UDC package guidelines for the LT6372IUDC-0.2#PBF.