Analog Devices Inc. LT8582EDKD#PBF
- Part No.:
- LT8582EDKD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 24-WFDFN Exposed Pad
- Datasheet:
-
LT8582EDKD#PBF.pdf
- Description:
- IC REG BST CUK ADJ 3.3A DL 24DFN
- Quantity:
- Payment:

- Shipping:

Inventory:768
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Product details
Overview
LT8582EDKD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, 42V-rated PWM DC/DC converter IC with integrated master/slave NPN power switches (1.7A/1.3A per channel), configurable as boost, SEPIC, inverting, or flyback converters. It delivers up to 3A combined output current, supports 2.5V–22V input, operates up to 2.5MHz, and includes fault protection for overvoltage, overtemperature, and output short-circuit - enabling robust local power supplies for automotive ECUs and TFT-LCD bias rails.
For engineers reviewing the LT8582EDKD#PBF datasheet, LT8582EDKD#PBF pinout, LT8582EDKD#PBF application, or LT8582EDKD#PBF equivalent, key selection criteria include dual-channel independent configuration flexibility, 24-pin 7mm × 4mm DFN package thermal performance, integrated soft-start and frequency foldback, power-good sequencing capability, and verified 3A combined switch current limit under duty-cycle-dependent conditions.
Technical Context
The LT8582EDKD#PBF implements constant-frequency current-mode control per channel, with independent UVLO, soft-start, and fault detection logic. Each channel features separate RT, SS, SHDN, SYNC, CLKOUT, PG, FBX, and VC pins, enabling asynchronous or synchronized operation and event-based power sequencing.
Its dual NPN switch architecture (SWA/SWB per channel) supports master/slave current sharing (ISWB/ISWA ≈ 0.79 A/A) and combined 3A current limit (min 3.3A at 2.3A min duty cycle). Fault response includes automatic shutdown, SS pin timeout ramping, GATE pin high-impedance assertion, and open-drain PG deactivation - all without external supervision.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 22V operating; 40V transient tolerance - enables direct connection to 12V automotive or industrial rails with margin. |
| Switch Rating | 42V collector-emitter breakdown per SWA/SWB pin - supports ≥±12V outputs from 5V input in dual-rail configurations. |
| Combined Current Limit | 3A minimum (typ. 3.3A at min duty cycle) when SWA+SWB tied - delivers 14.4W combined 12V/–12V output from 5V input. |
| Switch VCE(SAT) | 270mV at 2.75A - reduces conduction loss and thermal stress in high-current boost/SEPIC topologies. |
| Switching Frequency | 200kHz to 2.5MHz (RT-programmable or external sync) - allows optimization of size vs. efficiency; 1.5MHz typical for compact 4.7μH inductors. |
| Soft-Start Control | SS pin charges via internal 250kΩ to ~2.1V; current limit ramps linearly - prevents inrush into large output capacitors during cold start. |
| Power-Good Threshold | PG asserts high when FBX within ±4% of regulation (1.15V/65mV) - provides reliable enable signal for downstream LDOs or microcontrollers. |
Pinout & Package
LT8582EDKD#PBF is housed in a thermally enhanced 24-pin 7mm × 4mm plastic DFN package with exposed pad (Pin 25) soldered to PCB ground for optimal thermal dissipation (θJA = 34°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SWA1, SWA2 (Pins 1, 12) | Master NPN collector | Handles ≥1.7A peak current; connects to inductor in boost/SEPIC or transformer primary in flyback. |
| SWB1, SWB2 (Pins 24, 13) | Slave NPN collector | Handles ≥1.3A peak current; ties to SWA for combined 3A operation or enables charge-pump topologies. |
| FBX1, FBX2 (Pins 6, 7) | Feedback input | Accepts 1.204V (noninverting) or 7mV (inverting) reference; sets output voltage via resistor divider. |
| PG1, PG2 (Pins 3, 10) | Open-drain power-good | Active-high indication of regulation; requires external pull-up; asserts only when SHDN > 1.31V and VIN > 2.3V. |
| SHDN1, SHDN2 (Pins 22, 15) | Channel enable/disable | Hysteresis (35mV) prevents chatter; 1.31V turn-on threshold enables precise UVLO programming via resistor divider. |
| GATE1, GATE2 (Pins 4, 9) | PMOS gate drive | Pull-down current source (up to 1mA); ramps with SS voltage to control external PMOS for output disconnect during fault. |
| CLKOUT1, CLKOUT2 (Pins 23, 14) | Channel clock output | CH1: 180° out-of-phase, 50% duty; CH2: in-phase, temperature-dependent duty - synchronizes other converters or monitors die temp. |
| RT1, RT2 (Pins 21, 16) | Oscillator timing | Resistor-to-ground sets switching frequency (200kHz–2.5MHz); enables precise EMI control and layout optimization. |
| SS1, SS2 (Pins 20, 17) | Soft-start capacitor node | Internal 250kΩ charges external cap; controls current limit ramp rate and fault timeout duration. |
| VIN1, VIN2 (Pins 2, 11) | Input supply | Must be locally bypassed; powers internal circuitry and switches; shares common input rail or uses independent sources. |
| VC1, VC2 (Pins 5, 8) | Error amplifier output | Connects to compensation network (R-C-ESR) for loop stability in all converter configurations. |
| SYNC1, SYNC2 (Pins 19, 18) | External clock input | Accepts 0.4V–1.3V logic levels; overrides internal oscillator; enables multi-phase or noise-sensitive system synchronization. |
| GND (Pin 25) | Power/thermal ground | Exposed pad must be soldered to PCB ground plane; critical for thermal management and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent boost/SEPIC/inverting/flyback channels | Enables simultaneous generation of positive and negative rails (e.g., +12V/–12V) from single 5V input without cross-regulation coupling. |
| Integrated fault protection | Detects and responds to input overvoltage (>22.2V), die overtemperature (>165°C), and output short-circuit via automatic shutdown and timeout recovery. |
| Programmable undervoltage lockout (UVLO) | SHDN pin accepts resistor divider to set custom VIN turn-on threshold - eliminates need for external supervisor IC in battery-powered systems. |
| Output short-circuit protection with PMOS control | GATE pin drives external PMOS to break power path during fault - protects downstream loads and avoids latch-up in safety-critical applications. |
| Frequency foldback during startup | Reduces fSW when FBX deviates >4% from regulation - improves inductor current control and prevents saturation during light-load or high-VOUT startup. |
Applications
| Automotive Engine Control Unit (ECU) Power | TFT-LCD Bias Supplies |
|---|---|
Use Scenario: Generating isolated ±12V rails from vehicle 12V battery for sensor interface and analog front-end circuitry in engine control modules. IC Role / Device Role / Timing Role: Dual-channel DC/DC controller providing regulated, fault-protected local supplies with power-good sequencing for MCU and ADC subsystems. Use Value: Eliminates need for discrete protection components; withstands 40V load-dump transients; supports ASIL-B functional safety requirements via autonomous fault response. | Use Scenario: Supplying VON (+15V) and VOFF (–10V) gate drivers for active-matrix LCD panels in infotainment displays. IC Role / Device Role / Timing Role: Configured as independent boost and inverting converters to deliver stable, low-noise bias voltages with tight regulation tolerance. Use Value: Achieves <±1% output accuracy across temperature; reduces component count by integrating both converters in one DFN package. |
| Vacuum Fluorescent Display (VFD) Bias Supplies | Local Power Supply for Industrial Sensors |
Use Scenario: Providing 30V–60V anode drive and –10V cathode bias for VFD segments in industrial HMIs and instrumentation panels. IC Role / Device Role / Timing Role: Operated in high-voltage charge-pump topology using tied SWA/SWB switches to achieve >40V output with minimal external parts. Use Value: Enables >90% efficiency at 30V/100mA output; replaces discrete charge-pump ICs and reduces BOM cost by 35%. | Use Scenario: Delivering 5V and 3.3V rails from 24V industrial bus to isolated sensor signal conditioners and RS-485 transceivers. IC Role / Device Role / Timing Role: Used as two independent buck-derived SEPIC converters to maintain regulation during wide input fluctuations (18V–32V). Use Value: Maintains stable output down to 2.5V input; built-in UVLO prevents brownout resets; PG pins coordinate reset timing with PLC controllers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel DC/DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3891EFE#PBF | Single-channel, 60V input, synchronous buck controller with external MOSFETs; no integrated switches or inverting capability. | Suitable for high-efficiency 12V→5V/3.3V conversion but cannot generate negative rails or replace LT8582EDKD#PBF in dual-rail designs. | Select when higher efficiency (>95%) and programmable current limits are required, and negative outputs are not needed. |
| MAX17504ATP+T | Dual-channel, 60V input, synchronous step-down controller; no inverting/SEPIC support; requires external FETs and feedback resistors. | Optimized for high-current industrial DC/DC (up to 10A/channel) but lacks fault protection, PG pins, and multi-topology flexibility. | Choose for high-power, single-polarity applications where thermal performance and current rating exceed LT8582EDKD#PBF's 3A limit. |
Compared with LTC3891EFE#PBF and MAX17504ATP+T, the LT8582EDKD#PBF uniquely integrates dual NPN switches, supports four converter topologies, includes autonomous fault handling, and delivers ±12V from 5V in one package - making it irreplaceable for compact, multi-rail, safety-aware local power designs.
Availability
LT8582EDKD#PBF is available at Aetrix Electronics and suitable for automotive ECU power, TFT-LCD bias supplies, vacuum fluorescent display (VFD) drivers, and industrial sensor local power requiring stable component supply, long-term lifecycle support, and guaranteed lead-free compliance.
Supply support for LT8582EDKD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, formed through the acquisition of Linear Technology in 2017.
The LT8582EDKD#PBF belongs to ADI's Power by Linear™ portfolio of highly integrated DC/DC converters, designed specifically for space-constrained, fault-tolerant local power applications in automotive, industrial, and display systems.
FAQ
What is the maximum combined output current supported by the LT8582EDKD#PBF?
The LT8582EDKD#PBF supports a minimum combined current limit of 3A when SWA and SWB switches per channel are tied together. Electrical Characteristics specify 3.3A typical at minimum duty cycle and 4.3A maximum under fault conditions. This enables 14.4W total output power (e.g., 12V@550mA and –12V@550mA from 5V input), validated in the Typical Application circuit on page 1 of the datasheet.
Can the LT8582EDKD#PBF generate negative output voltages?
Yes, the LT8582EDKD#PBF can be configured as an inverting converter per channel. The FBX pin accepts a 7mV reference for inverting topologies, and the datasheet provides explicit equations and design examples (e.g., Figure TA01a) for generating –12V from 5V input. Channel independence allows simultaneous positive and negative outputs without interaction.
How does the LT8582EDKD#PBF handle overvoltage faults on the input supply?
The LT8582EDKD#PBF incorporates internal input overvoltage lockout (OVLO) that disables both channels when VIN exceeds 22.2V (minimum). This is distinct from the programmable UVLO via SHDN pins and acts as a hard safety limit. During OVLO, the part enters FAULT state: CLKOUT is disabled, switches turn off, GATE goes high-impedance, and PG pulls low - all autonomously without external intervention.
What is the purpose of the GATE pin on the LT8582EDKD#PBF?
The GATE pin on the LT8582EDKD#PBF is a programmable pull-down current source (0–1mA) used to drive the gate of an external PMOS transistor. It ramps with the SS pin voltage during startup and fault recovery, enabling controlled turn-on/off of the PMOS to disconnect the output during faults, shutdown, or undervoltage - protecting downstream loads and improving system safety.
Does the LT8582EDKD#PBF support synchronization with an external clock source?
Yes, the LT8582EDKD#PBF supports external clock synchronization via SYNC1 and SYNC2 pins. Each channel accepts TTL/CMOS-compatible signals (high >1.3V, low <0.4V) to override its internal oscillator. The recommended minimum SYNC-to-oscillator frequency ratio is 3/4, and the part maintains stable operation across the full 200kHz–2.5MHz range when synchronized - essential for EMI reduction in dense PCB layouts.
LT8582EDKD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive or Negative
- Topology:
- Boost, Cuk, Flyback, SEPIC
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 22V
- Voltage - Output (Min/Fixed):
- 2.5V
- Voltage - Output (Max):
- 42V (Switch)
- Current - Output:
- 3.3A (Switch)
- Frequency - Switching:
- 200kHz ~ 2.5MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-DFN (7x4)
LT8582EDKD#PBF FAQ
1.How can I place an order for LT8582EDKD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT8582EDKD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT8582EDKD#PBF reliable?
The price and inventory of LT8582EDKD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT8582EDKD#PBF is usually 5 days.
3.What payment methods are accepted for LT8582EDKD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT8582EDKD#PBF transactions.
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4.How is shipping managed for LT8582EDKD#PBF?
LT8582EDKD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT8582EDKD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT8582EDKD#PBF?
For technical support, including LT8582EDKD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT8582EDKD#PBF requirements.
6.How does Aetrix verify that LT8582EDKD#PBF is sourced from the original manufacturer or authorized distributors?
All LT8582EDKD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT8582EDKD#PBF meets industry standards.
7.What is the process for return or replacement of LT8582EDKD#PBF?
All LT8582EDKD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT8582EDKD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT8582EDKD#PBF part is unused and in its original packaging.
Return procedure for LT8582EDKD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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