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Analog Devices Inc. LT8582IDKD#PBF
- Part No.:
- LT8582IDKD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 24-WFDFN Exposed Pad
- Datasheet:
-
LT8582IDKD#PBF.pdf
- Description:
- IC REG BST CUK ADJ 3.3A DL 24DFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,080
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Product details
Overview
LT8582IDKD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, 42V, 3A combined current PWM DC/DC converter IC with integrated master/slave NPN switches, fault protection, and power-good signaling. It supports boost, SEPIC, inverting, and flyback topologies per channel, delivers ±12V at 550mA from 5V input, and operates across 2.5V–22V input range with up to 2.5MHz switching frequency.
For engineers reviewing the LT8582IDKD#PBF datasheet, LT8582IDKD#PBF pinout, LT8582IDKD#PBF application, or LT8582IDKD#PBF equivalent, this page provides verified technical context, validated pin functions, topology-specific design meaning, and confirmed alternative parts for local power supply, VFD bias, TFT-LCD bias, and automotive ECU power designs.
Technical Context
The LT8582IDKD#PBF implements constant-frequency current-mode control per channel, with independent UVLO, soft-start, and frequency foldback. Each channel integrates a 1.7A master switch (SWA) and 1.3A slave switch (SWB), configurable as separate or paralleled (3A total) with 270mV typical VCE(SAT) at 2.75A.
Fault detection includes output short-circuit (via sample-mode current sensing), input overvoltage (>22.2V), and junction overtemperature (>165°C). Power good (PG) pins assert high when FBX voltage is within ±4% of regulation target (1.204V for noninverting, 7mV for inverting), and CLKOUT pins support inter-IC synchronization-CH1 fixed 50% duty cycle, CH2 temperature-dependent duty cycle.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 22V operating; 40V transient max - enables direct use with 12V automotive rails and 5V logic supplies without pre-regulation. |
| Switch Rating | 42V collector-emitter max per SWA/SWB pin - supports ≥36V output in boost/SEPIC configurations with margin. |
| Combined Current Limit | 3A min (SWA+SWB tied) - delivers 14.4W combined ±12V output from 5V input in dual-rail applications. |
| Switching Frequency | 200kHz to 2.5MHz (adjustable via RT pin) - allows optimization for size (high-freq) or efficiency (mid-freq) in space-constrained PCBs. |
| VCE(SAT) | 270mV typ at 2.75A - reduces conduction loss and thermal rise in high-current switching paths. |
| Soft-Start Control | SS pin charges to ~2.1V via internal 250kΩ resistor - enables controlled inrush current ramp and hot-plug capability with external capacitor. |
| Power Good Threshold | PG asserts high when FBX = 1.15V–1.20V (noninverting) or FBX = 20–65mV (inverting) - provides reliable sequencing signal for downstream regulators or microcontrollers. |
Pinout & Package
LT8582IDKD#PBF is housed in a 24-pin 7mm × 4mm DFN package with exposed thermal pad (Pin 25 = GND), requiring soldering to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SWA1, SWA2 (Pins 1, 12) | Master NPN collector | Handles ≥1.7A peak current; connects to inductor node in boost/SEPIC/inverting topologies; low-inductance routing critical for EMI control. |
| SWB1, SWB2 (Pins 24, 13) | Slave NPN collector | Handles ≥1.3A peak current; ties to SWA for 3A combined limit or used independently for dual-output flyback. |
| FBX1, FBX2 (Pins 6, 7) | Feedback input | Accepts 1.204V reference for noninverting outputs or 7mV for inverting outputs; sets regulation point with 83.3μA bias current. |
| PG1, PG2 (Pins 3, 10) | Open-drain power-good | Active-high status indicating ±4% FBX regulation; requires external pull-up; valid only when SHDN > 1.31V and VIN > 2.3V. |
| SHDN1, SHDN2 (Pins 22, 15) | Channel enable/disable | Hysteresis of 35mV; 1.31V turn-on threshold enables precise UVLO programming via resistor divider from VIN. |
| GATE1, GATE2 (Pins 4, 9) | PMOS gate drive | Pull-down current source (0–1mA linear with SS voltage); drives external PMOS for output disconnect during fault or shutdown. |
| CLKOUT1, CLKOUT2 (Pins 23, 14) | Channel clock output | CH1: 180° out-of-phase, 50% duty cycle; CH2: in-phase, temperature-proportional duty cycle; drives ≤120pF load. |
| RT1, RT2 (Pins 21, 16) | Oscillator timing | Resistor-to-GND sets fSW; 31.6kΩ → 2.5MHz, 407kΩ → 200kHz - enables precise frequency selection without external crystal. |
| SS1, SS2 (Pins 20, 17) | Soft-start control | Charges to ~2.1V; controls ramp rate of switch current and GATE pull-down; enables inrush limiting and fault timeout sequencing. |
| VIN1, VIN2 (Pins 2, 11) | Input supply | Each channel has dedicated input pin; requires local 0.1μF ceramic bypass close to pin for stability and noise suppression. |
| VC1, VC2 (Pins 5, 8) | Error amplifier output | Connects to external compensation network (R-C-RC) for loop stability in all topologies; sets peak current reference. |
| SYNC1, SYNC2 (Pins 19, 18) | External clock input | Accepts 0.4V–1.3V logic levels; synchronizes channel to external source or cross-channels; reverts to internal oscillator if driven <0.4V. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent 42V, 3A combined power switches | Enables compact dual-rail (±12V) or dual-output (12V + 5V) local supplies without discrete MOSFETs or controllers. |
| Configurable undervoltage lockout (UVLO) | SHDN pin accepts resistor divider from VIN to set precise turn-on voltage (e.g., 8.5V UVLO with R1=100kΩ, R2=22kΩ). |
| Output short-circuit protection with sample-mode sensing | Detects overcurrent during startup or fault by sampling inductor current every cycle; triggers automatic shutdown without external sense resistors. |
| Integrated fault recovery with SS-based timeout | After fault, SS pin ramps up to 1.84V then discharges to 55mV - enforces minimum off-time for thermal recovery before retry. |
| High-gain SHDN pin with slow-signal tolerance | Accepts slowly ramping enable signals (e.g., from thermistors or RC delays); eliminates need for Schmitt-trigger buffers in sequencing circuits. |
Applications
| Vacuum Fluorescent Display (VFD) Bias Supply | TFT-LCD Bias Supply |
|---|---|
Use Scenario: Generating +30V and –30V bias rails for VFD segment/grid drivers in industrial HMIs and automotive instrument clusters. IC Role / Device Role / Timing Role: Dual-channel inverting/boost converter delivering regulated high-voltage rails with independent sequencing via PG pins. Use Value: Eliminates need for two discrete boost ICs or transformer-based solutions; 42V switch rating supports 30V output with margin; soft-start prevents display flicker during power-up. | Use Scenario: Providing AVDD (+15V), VGL (–10V), and VGH (+25V) for TFT-LCD source/gate drivers in medical monitors and portable displays. IC Role / Device Role / Timing Role: Configured as three independent converters (two channels + charge pump extension) with synchronized switching to minimize EMI coupling. Use Value: Reduces BOM count vs. multi-IC solutions; 2.5MHz operation allows small 4.7μH inductors; PG outputs coordinate power-up order to prevent latch-up. |
| Automotive Engine Control Unit (ECU) Power | Industrial Local Power Supply |
Use Scenario: Deriving isolated 5V and –5V auxiliary rails from 12V battery for CAN transceiver bias and sensor signal conditioning in under-hood ECUs. IC Role / Device Role / Timing Role: SEPIC-configured dual channel handling cold-crank (4.5V) to load-dump (36V) transients while maintaining regulation. Use Value: 40V absolute max input withstands automotive load dump; overvoltage lockout disables at 22.2V to protect downstream circuitry; thermal shutdown at 165°C prevents damage during prolonged overloads. | Use Scenario: Creating redundant 3.3V and 12V rails for FPGA I/O banks and analog front-ends in programmable logic controllers and test equipment. IC Role / Device Role / Timing Role: Boost + inverting configuration with external PMOS disconnect on GATE pins for fault-isolated power domains. Use Value: Output short protection isolates faults without blowing fuses; power-good signals feed FPGA configuration state machines; DFN package supports high-density layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel DC/DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3891EFE#PBF | Single-channel 60V synchronous buck controller; no integrated switches; requires external MOSFETs and inductor. | Designed for high-efficiency step-down only; lacks inverting/SEPIC capability and dual-channel integration. | Select when >95% efficiency at >5A load is required and board space allows discrete FETs and magnetics. |
| MAX20406AATG+T | Dual 3.6V–36V input, 3A/2A buck converters in 20-pin TQFN; no inverting/SEPIC support; no PG or fault reporting. | Optimized for automotive ADAS cameras; lacks high-voltage switch rating and topology flexibility. | Select for cost-sensitive 5V/3.3V dual-rail systems where input stays below 36V and only buck conversion is needed. |
Compared with LTC3891EFE#PBF and MAX20406AATG+T, the LT8582IDKD#PBF uniquely combines dual 42V integrated switches, inverting/SEPIC/boost/flyback configurability, and comprehensive fault protection in a single 24-pin DFN-making it the only choice for compact, high-voltage, multi-topology local power in space- and reliability-constrained designs.
Availability
LT8582IDKD#PBF is available at Aetrix Electronics and suitable for vacuum fluorescent display (VFD) bias supplies, TFT-LCD bias supplies, and automotive engine control unit (ECU) power applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LT8582IDKD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (including legacy Linear Technology products) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LT8582 product line delivers highly integrated dual-channel DC/DC converters for space-constrained, high-reliability local power generation-specifically engineered for applications demanding multiple isolated or complementary voltage rails from a single input source.
FAQ
What topologies can the LT8582IDKD#PBF support per channel?
The LT8582IDKD#PBF supports boost, SEPIC, inverting, and flyback configurations per channel. Each channel's master (SWA) and slave (SWB) switches can be used independently or tied together. The datasheet confirms operation in all four topologies with example schematics, including ±12V dual-rail output from 5V input using boost and inverting modes simultaneously.
Does the LT8582IDKD#PBF include overvoltage protection on the input?
Yes, the LT8582IDKD#PBF includes internal input overvoltage lockout (OVLO) that disables the device when VIN exceeds 22.2V (minimum). This is distinct from the configurable UVLO set via the SHDN pin and acts as a hard safety limit to protect internal circuitry during load-dump events or supply faults.
How does the LT8582IDKD#PBF implement output short-circuit protection?
The LT8582IDKD#PBF uses sample-mode current sensing: when FBX is out of regulation (>4%), the master and slave switches turn on briefly each cycle to sample inductor current. If sampled current exceeds 2A (SWA) or 3.5A (SWA+SWB), a fault is triggered, disabling switching, pulling PG low, and initiating SS-based timeout recovery-no external sense resistor required.
Can the LT8582IDKD#PBF synchronize its two channels to each other?
Yes, the LT8582IDKD#PBF supports inter-channel synchronization: SYNC1 can be driven by CLKOUT2, and SYNC2 can be driven by CLKOUT1. The datasheet explicitly states "Can also be used to synchronize channel 1 or channel 2 of the LT8582 with the other channel of the LT8582," enabling phase-controlled dual-output operation to reduce input ripple.
What is the thermal performance of the LT8582IDKD#PBF in its DFN package?
The LT8582IDKD#PBF DFN package has θJA = 34°C/W and θJC = 7°C/W. With the exposed pad (Pin 25) soldered to a 4-layer PCB's internal ground plane, it sustains continuous 3A combined switching current at ambient temperatures up to 85°C. Junction temperature is actively monitored, with overtemperature shutdown at 165°C (minimum) to prevent permanent damage.
LT8582IDKD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive or Negative
- Topology:
- Boost, Cuk, Flyback, SEPIC
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 22V
- Voltage - Output (Min/Fixed):
- 2.5V
- Voltage - Output (Max):
- 42V (Switch)
- Current - Output:
- 3.3A (Switch)
- Frequency - Switching:
- 200kHz ~ 2.5MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-DFN (7x4)
LT8582IDKD#PBF FAQ
1.How can I place an order for LT8582IDKD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT8582IDKD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT8582IDKD#PBF reliable?
The price and inventory of LT8582IDKD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT8582IDKD#PBF is usually 5 days.
3.What payment methods are accepted for LT8582IDKD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT8582IDKD#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT8582IDKD#PBF?
LT8582IDKD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT8582IDKD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT8582IDKD#PBF?
For technical support, including LT8582IDKD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT8582IDKD#PBF requirements.
6.How does Aetrix verify that LT8582IDKD#PBF is sourced from the original manufacturer or authorized distributors?
All LT8582IDKD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT8582IDKD#PBF meets industry standards.
7.What is the process for return or replacement of LT8582IDKD#PBF?
All LT8582IDKD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT8582IDKD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT8582IDKD#PBF part is unused and in its original packaging.
Return procedure for LT8582IDKD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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