Analog Devices Inc. LT8710EFE#PBF
- Part No.:
- LT8710EFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LT8710EFE#PBF.pdf
- Description:
- IC REG CTRLR MULT TOP 20TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT8710EFE#PBF from Analog Devices (formerly Linear Technology) is a synchronous PWM DC/DC controller supporting boost, SEPIC, inverting, and flyback topologies with rail-to-rail output current monitoring and control. It delivers 4.5V to 80V input range, 100kHz–750kHz adjustable switching frequency, and integrated C/10 or power-good indication via the FLAG pin-enabling precise lead-acid battery charging and automotive ECU power supplies.
For engineers reviewing the LT8710EFE#PBF datasheet, LT8710EFE#PBF pinout, LT8710EFE#PBF application, or LT8710EFE#PBF equivalent, key selection considerations include its dual-input LDO (INTVCC/INTVEE), EN/FBIN input voltage regulation capability, MODE-selectable forced CCM vs pulse-skipping operation, and 20-lead TSSOP package with exposed thermal pad.
Technical Context
The LT8710EFE#PBF implements a constant-frequency, current-mode control architecture with three independent error amplifiers (EA1 for positive FBX regulation, EA2 for negative FBX, EA3 for IMON current sense) and dedicated transconductance amplifiers for ISP/ISN and EN/FBIN inputs. Its gate drivers (BG/TG) support synchronous FET switching with non-overlap timing and minimum on/off times validated down to 150ns.
It integrates dual low-dropout regulators: INTVCC (6.3V, 5mA max load) sourced from VIN or BIAS, and INTVEE (BIAS – 6.18V, 10mA max) for TG driver biasing. The EN/FBIN pin provides programmable UVLO, input voltage regulation, and chip enable with 44mV hysteresis, while the MODE pin selects between forced continuous conduction mode (CCM) and discontinuous/pulse-skipping operation based on 1.175V/1.224V thresholds.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 80V - supports wide-range industrial, automotive, and solar inputs without external pre-regulation |
| Switching Frequency | 100kHz to 750kHz - set via RT resistor or synchronized externally; foldback to 20% during overload |
| Output Current Sense Accuracy | ±7mV offset at 50mV full-scale - enables precise 1% current limiting across temperature |
| FBX Regulation Voltage | 1.213V ±2.6mV - stable reference for both positive and negative output configurations |
| Quiescent Current | 4mA typical (not switching) - low standby power for always-on systems |
| Package | 20-lead TSSOP with exposed thermal pad - 38°C/W θJA enables >5A output designs with standard PCB copper |
| Operating Temperature | –40°C to 125°C junction - qualified for under-hood automotive and industrial environments |
Pinout & Package
LT8710EFE#PBF is housed in a 20-lead plastic TSSOP package (FE grade) with an exposed thermal pad (Pin 21) that must be soldered to the PCB ground plane for thermal and electrical integrity. Pin pitch is 0.65mm; body dimensions are 6.5mm × 4.4mm × 1.1mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FBX (1) | Feedback Input | Accepts positive or negative output voltage feedback; 1.213V reference enables boost/SEPIC/inverting configurations with single-resistor divider |
| VC (2) | Error Amplifier Output | Compensation node for loop stability; connects to external RC network for type-II/type-III compensation |
| SS (3) | Soft-Start Control | Charges to ~2.7V via internal 260kΩ; discharge triggers reset during overcurrent, UVLO, or overtemperature |
| FLAG (4) | Status Output | Active-high open-drain indicator for power-good (FBX >1.153V) or C/10 charge termination (ISP–ISN <5mV) |
| IMON (5) | Current Monitor Output | Voltage output proportional to ISP–ISN: VIMON = 11.9×(VISP–VISN+51.8mV); requires 10–100nF filter capacitor |
| ISN / ISP (6,7) | Current Sense Inputs | Kelvin-connected to sense resistor; commands NFET current limit at 50mV differential (typical) |
| BIAS (8) | Alternate Supply / PFET Bias | Sets TG driver high rail; connect to VOUT (positive) or INTVCC (negative) for proper gate drive swing |
| INTVEE (9) | TG Driver Bottom Rail | 6.18V below BIAS; must be bypassed with ≥2.2µF to BIAS; enables TG switching when BIAS–INTVEE >3.42V |
| TG (10) | PFET Gate Driver | Outputs BIAS (high) and BIAS–INTVEE (low); rise/fall times <16ns into 3300pF |
| BG (11) | NFET Gate Driver | Outputs INTVCC (high) and GND (low); rise/fall times <24ns into 3300pF; non-overlap time 45–220ns |
| INTVCC (12) | Dual-Input LDO Output | 6.3V regulator powered from VIN or BIAS; 4V UVLO threshold enables BG driver startup |
| VIN (13) | Main Input Supply | Primary power source; can be 0V if BIAS ≥4.5V - supports biased-start architectures |
| CSP / CSN (14,15) | NFET Current Sense | Kelvin-connected to NFET source/sense resistor; limits peak switch current to 50mV at low duty cycle |
| EN/FBIN (16) | Enable / Input Regulation | Three-function pin: chip enable (1.7V), UVLO (1.3V), and input voltage regulation (1.607V); 44mV hysteresis prevents chatter |
| MODE (17) | CCM/DCM Selection | Forces CCM below 1.175V (typ), enables DCM/pulse-skipping above 1.224V (typ); hysteresis 49mV |
| RT (18) | Oscillator Timing | Connects to GND via resistor to set fSW; 46.4kΩ → 640kHz, 357kΩ → 85kHz |
| SYNC (19) | External Clock Input | Accepts 0.4V–1.5V logic levels; synchronizes switching to external clock with ≥75% duty cycle tolerance |
| GND (20) | Analog Ground | Reference for all analog circuitry; separate from exposed pad (Pin 21) |
| GND (21) | Thermal Pad | Exposed copper pad; must be soldered to PCB ground plane for thermal dissipation and noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail output current monitor and control | Enables accurate battery charging with C/10 termination and real-time current telemetry via IMON pin |
| Single feedback pin for multiple topologies | FBX pin supports boost, SEPIC, inverting, and flyback with unified regulation equations and no external mode switches |
| Input voltage regulation via EN/FBIN | Prevents collapse of high-impedance sources (e.g., solar panels) by dynamically limiting input current |
| Forced CCM or pulse-skipping via MODE pin | Eliminates light-load efficiency drop in CCM mode or reduces audible noise in DCM mode |
| Integrated dual LDOs (INTVCC and INTVEE) | Provides independent, regulated rails for BG and TG drivers-enabling robust gate drive across input voltage extremes |
| Frequency foldback during overload | Reduces switching losses and thermal stress by scaling fSW to 20% of nominal during fault conditions |
Applications
| Automotive Engine Control Unit (ECU) Power | Lead-Acid Battery Charger |
|---|---|
Use Scenario: Powering 5V/3.3V microcontrollers and sensors in vehicle engine bays where input ranges from 6V (cold crank) to 16V (load dump). IC Role / Device Role / Timing Role: Synchronous SEPIC controller regulating stable 5V output from unregulated battery rail; uses EN/FBIN for input voltage regulation during cranking. Use Value: Maintains system uptime during 6V–16V transients; rail-to-rail current sensing ensures safe charging of auxiliary 12V batteries. | Use Scenario: Charging 12V sealed lead-acid batteries from 12V–24V solar or vehicle alternator sources with bulk/float transition. IC Role / Device Role / Timing Role: Inverting or SEPIC controller with FLAG pin configured as C/10 indicator to terminate bulk charge and initiate float stage. Use Value: Achieves ±1% voltage regulation and precise 10% current cutoff-extending battery life and preventing overcharge damage. |
| High-Power Local Power Supply | Wide-Input SEPIC/Inverting Converter |
Use Scenario: Generating isolated or non-isolated 5V/12V rails in industrial PLCs requiring >3A output from 12V–48V backplane supplies. IC Role / Device Role / Timing Role: Boost controller driving external MOSFETs with synchronous rectification; uses MODE pin for forced CCM to minimize output ripple. Use Value: Delivers >94% efficiency at full load; thermal pad and low RDS(on) gate drivers sustain continuous 5A output without derating. | Use Scenario: Converting 4.5V–25V input to –5V output for analog sensor interfaces or op-amp biasing in mixed-signal instrumentation. IC Role / Device Role / Timing Role: Inverting controller using FBX for negative feedback; employs INTVEE tied to GND and BIAS to VOUT for proper TG biasing. Use Value: Eliminates need for external inverting charge pumps; achieves <100mV output ripple and fast transient response via current-mode control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous DC/DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3780EFE#PBF | Single-output synchronous buck-boost controller; no inverting topology support; lacks IMON current monitor output | Best suited for 4V–36V buck-boost applications where negative output or C/10 battery charging is not required | Select LTC3780EFE#PBF only when topology is strictly buck-boost and current telemetry is unnecessary |
| LM5122MMX/NOPB | Non-synchronous boost/SEPIC controller; no TG driver or INTVEE regulator; lower max input voltage (65V) | Appropriate for cost-sensitive, lower-power (<2A) boost converters where synchronous efficiency is secondary | Choose LM5122MMX/NOPB for simpler designs without inverting capability or precision current monitoring |
Compared with LTC3780EFE#PBF and LM5122MMX/NOPB, the LT8710EFE#PBF uniquely supports inverting, SEPIC, boost, and flyback topologies in one IC, includes rail-to-rail current monitoring with IMON output, and integrates dual LDOs for robust gate drive-making it the only option for high-accuracy battery charging and wide-input negative-output applications.
Availability
LT8710EFE#PBF is available at Aetrix Electronics and suitable for automotive ECU power, lead-acid battery chargers, and high-power local power supplies requiring stable component supply across extended temperature and voltage ranges.
Supply support for LT8710EFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors.
The LT8710EFE#PBF belongs to Linear's high-voltage synchronous controller product line, designed specifically for flexible, high-efficiency DC/DC conversion in automotive, industrial, and renewable energy systems where wide input range and topology versatility are critical.
FAQ
What topologies does the LT8710EFE#PBF support?
The LT8710EFE#PBF supports boost, SEPIC, inverting, and flyback topologies using a single feedback pin (FBX) and configurable gate drivers. Its rail-to-rail current sensing, dual LDOs (INTVCC/INTVEE), and MODE pin enable seamless reconfiguration without changing external components. This makes LT8710EFE#PBF ideal for multi-rail power designs where board space and BOM count are constrained.
How does the FLAG pin function in the LT8710EFE#PBF?
The FLAG pin on the LT8710EFE#PBF serves dual roles: as an active-high power-good indicator (triggered when FBX crosses 1.153V with 58mV hysteresis) or as a C/10 battery charge termination signal (activated when ISP–ISN falls below 5mV). A 100µs anti-glitch delay prevents false triggering. External pull-up is required. This dual functionality is integral to LT8710EFE#PBF's use in precision battery charging systems.
Can the LT8710EFE#PBF operate with input voltages below 4.5V?
No-the LT8710EFE#PBF has a minimum operating input voltage of 4.5V when powered from VIN, but it can start and operate with VIN = 0V if the BIAS pin is supplied ≥4.5V. This bias-powered operation allows LT8710EFE#PBF to function in architectures where the main input is unavailable at startup (e.g., solar chargers with auxiliary bias supply).
What is the purpose of the EN/FBIN pin on the LT8710EFE#PBF?
The EN/FBIN pin on the LT8710EFE#PBF provides three functions: chip enable (1.7V threshold), undervoltage lockout (1.3V threshold), and input voltage regulation (1.607V threshold). It accepts slowly varying signals and features 44mV hysteresis. This enables LT8710EFE#PBF to regulate input current and prevent collapse of high-impedance sources like photovoltaic panels or long cables.
Does the LT8710EFE#PBF require external compensation components?
Yes-the LT8710EFE#PBF requires external compensation components connected to the VC pin to stabilize the control loop. A type-II or type-III network (typically RC + C or R + RC) is used depending on topology and bandwidth requirements. The datasheet provides design equations and example values for boost, SEPIC, and inverting configurations-essential for reliable LT8710EFE#PBF implementation.
LT8710EFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Up, Step-Down, Step-Up/Step-Down
- Output Configuration:
- Positive or Negative
- Topology:
- Boost, Flyback, SEPIC
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 80V
- Frequency - Switching:
- 100kHz ~ 750kHz
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Enable, Frequency Control, Soft Start
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP-EP
LT8710EFE#PBF FAQ
1.How can I place an order for LT8710EFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT8710EFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT8710EFE#PBF reliable?
The price and inventory of LT8710EFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT8710EFE#PBF is usually 5 days.
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Once your LT8710EFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT8710EFE#PBF?
For technical support, including LT8710EFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT8710EFE#PBF requirements.
6.How does Aetrix verify that LT8710EFE#PBF is sourced from the original manufacturer or authorized distributors?
All LT8710EFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT8710EFE#PBF meets industry standards.
7.What is the process for return or replacement of LT8710EFE#PBF?
All LT8710EFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT8710EFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT8710EFE#PBF part is unused and in its original packaging.
Return procedure for LT8710EFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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