Analog Devices Inc. LTC1235CN#PBF
- Part No.:
- LTC1235CN#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
LTC1235CN#PBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:101
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Product details
Overview
LTC1235CN#PBF from Analog Devices (formerly Linear Technology) is a microprocessor supervisory circuit integrating power monitoring, conditional battery backup, RAM write protection, power-fail warning, and watchdog timing. It guarantees reset assertion down to VCC = 1V, delivers up to 50mA from VOUT with ≤5Ω on-resistance, and provides 4.65V precision voltage monitoring with 40mV hysteresis - used in battery-powered industrial controllers requiring reliable brownout recovery and data retention.
For engineers reviewing the LTC1235CN#PBF datasheet, LTC1235CN#PBF pinout, LTC1235CN#PBF application, or LTC1235CN#PBF equivalent, key selection criteria include guaranteed 1V reset operation, programmable conditional battery backup (via BACKUP pin latching), fast 35ns CE gating, 200ms reset timeout, and integrated PFI/PFO comparator for early power-fail detection.
Technical Context
The LTC1235CN#PBF implements a dual-path power switch architecture: an NMOS M1 (5Ω typical RDS(on)) supplies VOUT from VCC during normal operation, while a PMOS M2 (125Ω typical RDS(on)) enables battery switchover when VCC falls below VBATT - conditioned by the latched logic state of the BACKUP pin at reset threshold crossing. Its internal 1.3V reference drives the PFI comparator for user-configurable power-fail warning, and its watchdog timer triggers RESET/WDO on WDI stall exceeding 1.0–2.25s.
Reset generation is triple-redundant: triggered by VCC falling below 4.65V (±100mV), by PB RST debounced low ≥40ms, or by watchdog timeout; all force RESET low for ≥140ms post-event. The CE IN/CE OUT gating circuit enforces RAM write-protection by forcing CE OUT high whenever VCC drops below reset threshold or VBATT, independent of CE IN state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Voltage Threshold | 4.65V typical, ±100mV tolerance - ensures deterministic μP reset before 5V rail collapse compromises logic integrity. |
| VOUT Output Current | 50mA max from VCC via M1 - sufficient to power small SRAM banks without external boost. |
| Battery Switchover Threshold | VCC – VBATT = 50mV (power-down), 70mV (power-up) - minimizes dropout while preventing oscillation near crossover. |
| CE Propagation Delay | 20–35ns - enables real-time RAM write-gating synchronized with μP address decoding. |
| Watchdog Timeout Period | 1.0–2.25s - configurable via external clock or WDI toggling; prevents runaway code without CPU intervention. |
| Standby Supply Current | 1μA max - extends shelf life of battery-backed systems during long-term storage. |
| Power Fail Input Threshold | 1.30V ±10mV - allows precise early-warning trip point using external resistor divider on PFI. |
Pinout & Package
Package: 16-Lead Plastic DIP (N package), 0°C to 70°C operating range, lead-free finish (PBF).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VBATT | Backup battery input | Accepts 2.0–4.25V auxiliary supply; source for VOUT during power loss only if BACKUP pin latched high. |
| 2 VOUT | Backed-up memory output | Delivers up to 50mA from VCC (M1) or VBATT (M2); bypass with ≥0.1μF capacitor for stability. |
| 3 VCC | +5V main supply input | Primary power source; must be bypassed with 0.1μF capacitor; reset asserted down to 1V. |
| 4 GND | Ground reference | Common return for all analog/digital functions; critical for comparator accuracy and noise immunity. |
| 5 BATT ON | Battery-on logic output | Sinks 35mA; drives external PNP transistor base to extend VOUT current beyond 50mA. |
| 6 LOW LINE | Low-line indicator output | Active-low signal indicating VCC < 4.65V; used for system-level power status monitoring. |
| 7 PB RST | Debounced push-button reset input | Active-low, internally debounced ≥40ms; triggers guaranteed 140ms RESET pulse. |
| 8 BACKUP | Conditional backup control input | Latched at VCC crossing 4.65V; determines whether M2 activates during power loss. |
| 9 PFI | Power-fail input | Non-inverting input to 1.3V comparator; accepts voltage divider for user-defined fail threshold. |
| 10 PFO | Power-fail output | Active-low open-drain output; interrupts μP to initiate graceful shutdown before RESET asserts. |
| 11 WDI | Watchdog input | Three-level input (high/low/floating); timeout disables watchdog; transitions reset timer. |
| 12 CE OUT | Chip-enable output | Buffered CE IN replica during valid VCC; forced high during reset to prevent RAM writes. |
| 13 CE IN | Chip-enable input | Accepts μP address decoder output; propagation delay 20–35ns ensures timing-critical gating. |
| 14 WDO | Watchdog output | Active-low logic output mirroring RESET behavior during watchdog timeout. |
| 15 RESET | Active-low reset output | Guaranteed low down to VCC = 1V; holds μP in reset until power stabilizes and timeout expires. |
| 16 RESET | Active-high reset output | Inverse of pin 15; provides complementary signal for mixed-logic interface requirements. |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed reset at VCC = 1V | Ensures μP remains held in known state even during deep brownout, preventing undefined execution. |
| Conditional battery backup | BACKUP pin latching enables selective RAM backup - eliminates unnecessary battery drain during storage or shipping. |
| Fast 35ns CE gating | Prevents partial writes to SRAM during power transition, preserving data integrity without external logic. |
| Integrated PFI/PFO comparator | 1.3V reference + user-adjustable threshold provides early power-fail warning with <2μs response time. |
| Thermal limiting & short-circuit protection | Shuts down M1/M2 above ~155°C with 10°C hysteresis; limits VOUT output to ~200mA to prevent damage. |
Applications
| Industrial Data Loggers | Medical Portable Monitors |
|---|---|
|
Use Scenario: Battery-powered field loggers capturing sensor data over weeks; must retain RAM contents during intermittent AC loss or battery replacement. IC Role / Device Role / Timing Role: Supervisory controller managing VOUT switchover, latching backup enable, and asserting RESET to halt logging during undervoltage. Use Value: Conditional backup extends lithium coin-cell life by >3× versus always-on schemes; 1V reset guarantee prevents corrupted timestamp buffers. |
Use Scenario: Handheld ECG monitors with nonvolatile RAM storing patient waveforms; requires zero-data-loss power transition during battery swap. IC Role / Device Role / Timing Role: Dual-role supervisor: powers RAM via VOUT, gates CE to freeze memory access during brownout, and triggers PFO interrupt for waveform save-to-flash. Use Value: 200ms reset timeout aligns with clinical device boot requirements; 40mV hysteresis prevents false resets from line noise. |
| Automotive Infotainment Head Units | Ruggedized Tablet PCs |
|
Use Scenario: In-vehicle navigation units exposed to wide temperature swings and ignition-cycle voltage transients. IC Role / Device Role / Timing Role: Power integrity manager monitoring 5V rail, detecting load-dump events via PFI, and enforcing safe shutdown via WDI-triggered RESET. Use Value: PB RST debounce rejects contact bounce from mechanical switches; thermal shutdown protects against under-dash ambient heat. |
Use Scenario: Military-spec tablets used in field deployments where primary power may disconnect unexpectedly during active use. IC Role / Device Role / Timing Role: System-level guardian providing RAM backup, watchdog supervision, and coordinated RESET/PFO signaling for OS-level suspend. Use Value: 50mA VOUT drive supports larger SRAM arrays than competing supervisors; BATT ON output enables external boost for flash programming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691ACPP+ | Fixed 4.65V reset threshold; no conditional battery backup; 100μA quiescent current vs. 1μA. | Lacks programmable backup control and PFI/PFO comparator; suitable only for basic reset-only designs. | Select when conditional backup and early power-fail warning are unnecessary and cost is primary constraint. |
| TPS3823-46DBVR | 4.63V reset threshold; no VOUT power switch or battery switchover; no CE gating or watchdog timer. | Provides only reset and power-ok functions; cannot replace LTC1235CN#PBF's RAM backup or memory protection roles. | Choose only for simple reset supervision where VOUT, CE, and backup features are handled externally. |
Compared with MAX691ACPP+ and TPS3823-46DBVR, the LTC1235CN#PBF uniquely integrates conditional battery backup, RAM write-protection gating, and power-fail warning in a single 16-pin DIP - eliminating 3–4 discrete components and enabling true data-retentive brownout recovery.
Availability
LTC1235CN#PBF is available at Aetrix Electronics and suitable for industrial data loggers, medical portable monitors, automotive infotainment head units, ruggedized tablet PCs, and battery-powered instrumentation requiring stable component supply across extended lifecycle programs.
Supply support for LTC1235CN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full technical and manufacturing continuity for legacy Linear products including the LTC1235 series.
The LTC1235CN#PBF belongs to Linear's μP supervisory IC family, designed specifically for robust power monitoring and data retention in battery-critical embedded systems - emphasizing guaranteed low-voltage reset, minimal standby current, and integrated memory protection.
FAQ
What is the guaranteed minimum VCC voltage at which LTC1235CN#PBF asserts RESET?
The LTC1235CN#PBF guarantees RESET remains logic low down to VCC = 1V, ensuring microprocessor holdover during severe brownout conditions. This specification is tested and guaranteed over the full 0°C to 70°C operating temperature range, enabling reliable operation in systems where input voltage may sag significantly before complete failure. The LTC1235CN#PBF achieves this via dedicated low-voltage sensing circuitry independent of the main bandgap reference.
How does the conditional battery backup function work in LTC1235CN#PBF?
The LTC1235CN#PBF latches the logic state of the BACKUP pin (Pin 8) as VCC crosses the 4.65V reset threshold during power-down. If latched high, the internal PMOS switch M2 connects VBATT to VOUT when VCC falls within 50mV of VBATT; if latched low, M2 stays off and VOUT enters Battery Saving Mode. This mechanism extends battery life by disabling backup only when RAM data preservation is unnecessary - a feature not present in standard supervisors like the MAX691 or TPS3823. The LTC1235CN#PBF implements this entirely on-chip with no external components required.
What is the purpose of the CE IN and CE OUT pins on LTC1235CN#PBF?
CE IN (Pin 13) accepts a microprocessor-derived chip-enable or address-decoder signal, while CE OUT (Pin 12) provides a buffered, glitch-free replica during normal operation - with 20–35ns propagation delay. Crucially, when VCC drops below 4.65V or VBATT, CE OUT is forced high regardless of CE IN state, preventing write operations to battery-backed CMOS RAM during unstable power. This hardware-enforced write protection ensures data integrity without software intervention. The LTC1235CN#PBF uses this gating to safeguard SRAM, EEPROM, and NOVRAM in mission-critical applications.
Can LTC1235CN#PBF monitor power supplies other than +5V?
Yes - the PFI (Pin 9) input accepts an externally scaled voltage via resistor divider, allowing monitoring of any DC rail. With its internal 1.30V reference, the LTC1235CN#PBF can detect failure of unregulated inputs (e.g., 12V automotive) or regulated outputs (e.g., 3.3V logic rails) by setting the divider ratio so PFI falls below 1.30V several milliseconds before the monitored rail violates its specification. The PFO output then provides early warning to the microprocessor for controlled shutdown. This flexibility makes the LTC1235CN#PBF adaptable beyond standard 5V systems while maintaining the same timing and accuracy specs.
What thermal protection mechanisms does LTC1235CN#PBF include?
The LTC1235CN#PBF incorporates thermal limiting that disables the internal NMOS (M1) and PMOS (M2) power switches when junction temperature exceeds ~155°C, with ~10°C hysteresis to prevent oscillation. It also features short-circuit current limiting on VOUT, clamping output to ~200mA under overload. These protections operate independently of VCC level and remain active even during battery backup mode. Combined with the 500mW maximum power dissipation rating and 130°C/W junction-to-ambient thermal resistance, these features ensure safe operation in enclosed or high-ambient environments - a critical requirement for the LTC1235CN#PBF's target applications in industrial and automotive settings.
LTC1235CN#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Open Drain, Open Drain
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
LTC1235CN#PBF FAQ
1.How can I place an order for LTC1235CN#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1235CN#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1235CN#PBF reliable?
The price and inventory of LTC1235CN#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1235CN#PBF is usually 5 days.
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Once your LTC1235CN#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1235CN#PBF?
For technical support, including LTC1235CN#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1235CN#PBF requirements.
6.How does Aetrix verify that LTC1235CN#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1235CN#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1235CN#PBF meets industry standards.
7.What is the process for return or replacement of LTC1235CN#PBF?
All LTC1235CN#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1235CN#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1235CN#PBF part is unused and in its original packaging.
Return procedure for LTC1235CN#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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