Analog Devices Inc. LTC1261CS#TRPBF

Overview

LTC1261CS#TRPBF from Analog Devices (formerly Linear Technology) is a switched-capacitor regulated voltage inverter IC that generates a stable negative output from a single 3V–8V positive supply. It delivers up to 12mA output current with ±5% regulation, 5mV typical output ripple, and features an open-drain REG pin indicating regulation status. It operates in doubler or tripler mode and supports fixed (–3.5V/–4V/–4.5V/–5V) or adjustable (–1.25V to –8V) outputs - ideal for GaAs FET biasing and battery-powered systems requiring clean negative rails.

For engineers reviewing the LTC1261CS#TRPBF datasheet, LTC1261CS#TRPBF pinout, LTC1261CS#TRPBF application, or LTC1261CS#TRPBF equivalent, key selection considerations include its 14-lead SOIC package, tripler-mode capability for –5V from 3.3V input, shutdown current of 5µA, internal resistor string for pin-strapped outputs, and compatibility with ceramic flying capacitors (0.1µF) and ≥3.3µF output bypass.

Technical Context

The LTC1261CS#TRPBF implements a charge-pump-based inverting regulator with dual operational modes: doubler mode (V_OUT ≈ –V_CC) and tripler mode (|V_OUT| ≤ 2×V_CC). Its regulation loop compares a divided output voltage at the ADJ pin against a 1.24V internal reference referenced to V_OUT, enabling precise feedback control independent of ground potential.

It integrates an internal oscillator (550kHz), on-chip resistor string (R0/R1/RADJ) for fixed-output configuration without external resistors, and dual comparators - one for regulation (COMP1) and another (COMP2, 1.18V threshold) driving the open-drain REG output when output is within ±5% of setpoint. The device requires no inductors and uses only ceramic capacitors for full operation.

Key Specifications

Pinout & Package

The LTC1261CS#TRPBF is housed in a 14-lead narrow-body plastic SOIC (SO-14) package with exposed pad not present; thermal resistance θ_JA = 110°C/W. Pin 1 is NC (no internal connection); pins C1+/C1–/C2+/C2– support tripler-mode flying capacitor routing; R0/R1/RADJ enable internal resistor string configuration; ADJ serves as feedback/compensation node; REG is open-drain status output.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar regulated negative voltage inverter applications.

Compared with MAX680ESA+ and LTC7149EMSE#PBF, the LTC1261CS#TRPBF uniquely balances capacitor-only simplicity, pin-strapped flexibility, and built-in power-good signaling - making it optimal for space-constrained, low-to-moderate current applications where inductor avoidance and system visibility are critical.

Availability

LTC1261CS#TRPBF is available at Aetrix Electronics and suitable for GaAs FET bias generators, portable medical sensors, single-supply op-amp rails, and IoT data converter interfaces requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for LTC1261CS#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.

The LTC1261CS#TRPBF belongs to ADI's legacy Linear Technology switched-capacitor power management product line, designed specifically for capacitor-based DC/DC conversion in space- and cost-sensitive applications where inductors are impractical.

FAQ

What is the maximum input voltage the LTC1261CS#TRPBF can tolerate?

The LTC1261CS#TRPBF has an absolute maximum supply voltage rating of 9V. However, safe operation requires limiting total V_CC–V_OUT differential to ≤12V. For example, with a 5V input, output must not exceed –7V; with 8V input, output must be ≥–4V to avoid exceeding ratings. Always consult the Absolute Maximum Ratings table and derate for temperature.

Can the LTC1261CS#TRPBF generate –5V from a 3.3V supply?

Yes, the LTC1261CS#TRPBF can generate –5V from a 3.3V supply using tripler mode, which achieves |V_OUT| ≈ 2×V_CC. This requires connecting two 0.1µF flying capacitors (C1 between C1+/C1–, C2 between C2+/C2–) and using the 14-lead SOIC package. Output regulation holds to ±5% at up to 10mA load under these conditions.

How does the REG pin on the LTC1261CS#TRPBF function?

The REG pin on the LTC1261CS#TRPBF is an open-drain output that pulls low when the magnitude of V_OUT is within 5% of the programmed value (e.g., –4.75V to –5.25V for a –5V setpoint). It sinks up to 8mA at 5V V_CC and tolerates pull-up voltages up to 12V. An external pull-up resistor is mandatory for high-state operation - no internal pull-up exists.

What external capacitors are required for basic operation of the LTC1261CS#TRPBF?

For basic doubler-mode operation, the LTC1261CS#TRPBF requires: one 0.1µF ceramic flying capacitor (C1 between C1+ and C2–), one ≥0.5µF ceramic input bypass capacitor on VCC, and one ≥3.3µF ceramic output capacitor on OUT. In tripler mode, add a second 0.1µF flying capacitor (C2 between C2+ and C2–). A 100pF compensation capacitor from ADJ to GND further reduces ripple.

Is the LTC1261CS#TRPBF pin-compatible with the LTC1261CS8#TRPBF?

No, the LTC1261CS#TRPBF (14-pin SOIC) is not pin-compatible with the LTC1261CS8#TRPBF (8-pin SOIC). The 14-pin version includes dedicated C2+, C2–, R0, R1, RADJ, and NC pins for tripler mode and internal resistor string configuration, while the 8-pin version consolidates functionality into fewer pins and lacks tripler-mode capability. PCB layout and schematic must be redesigned for interchange.