Analog Devices Inc. LTC1279CG#PBF
- Part No.:
- LTC1279CG#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 24-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC1279CG#PBF.pdf
- Description:
- IC ADC 12BIT SAR 24SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1279CG#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 600ksps successive-approximation analog-to-digital converter with internal reference, synchronized clock, and power shutdown. It operates from single 5V or ±5V supplies, delivers 70dB S/(N+D) at 100kHz, consumes 60mW typical, and supports unipolar (0V–5V) or bipolar (±2.5V) input ranges. It is used in high-speed data acquisition systems requiring low-power, high-accuracy sampling.
For engineers reviewing the LTC1279CG#PBF datasheet, LTC1279CG#PBF pinout, LTC1279CG#PBF application, or LTC1279CG#PBF equivalent, key selection criteria include guaranteed ±1LSB INL/DNL, 1.4µs conversion time, 24-pin SO wide package compatibility, and flexible parallel interface timing for DSP/microprocessor interfacing.
Technical Context
The LTC1279CG#PBF implements a 12-bit capacitive DAC-based successive approximation register (SAR) architecture with integrated sample-and-hold (160ns acquisition), factory-trimmed internal 2.42V reference, and self-synchronizing internal clock-eliminating external clock requirements. Its control logic supports mode 2 parallel readout with CS, RD, CONVST, and BUSY signals.
It features high-impedance analog input (±1µA leakage), three-state digital outputs (D11–D0), and independent analog/digital ground pins (AGND/DGND) to minimize noise coupling. Power shutdown reduces current to 1.7mA while enabling 350ns wake-up, making it suitable for burst-mode acquisition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes-guarantees monotonic transfer function for precision measurement. |
| Sampling Rate | 600ksps maximum-enables Nyquist-limited bandwidth up to 300kHz for real-time signal capture. |
| S/(N + D) | 70dB at 100kHz input-supports >11.6 effective bits for high-fidelity spectral analysis. |
| INL / DNL | ±1LSB max-ensures accurate code transition alignment across full scale, critical for calibration-sensitive systems. |
| Power Dissipation | 60mW typ at 600ksps; 8.5mW in shutdown-reduces thermal load and enables battery-powered portable instrumentation. |
| Conversion Time | 1.4µs typ-defines minimum throughput interval and sets timing budget for controller interface design. |
| Analog Input Range | 0V to 5V (unipolar) or ±2.5V (bipolar)-matches standard sensor output levels and differential signal chains. |
Pinout & Package
Package: 24-lead plastic SO wide (SW), 0.300" body width, RoHS-compliant lead finish (Pb-free).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN (1) | Analog Input | High-impedance node accepting 0V–5V or ±2.5V signals; requires low-noise drive and short trace routing. |
| VREF (2) | Reference Output | 2.42V ±20mV buffered reference; must be bypassed with 10µF + 0.1µF to AGND for stability. |
| AGND (3) | Analog Ground | Single-point return for analog circuitry; isolated from DGND to prevent digital noise injection. |
| D11–D4 (4–11) | Data Outputs (MSB-first) | Three-state parallel bus outputs; active when CS=RD=LOW and BUSY=HIGH. |
| DGND (12) | Digital Ground | Return path for digital I/O; connected to system digital ground, not AGND. |
| D3–D0 (13–16) | Data Outputs (LSB) | Completes 12-bit word; D0 is LSB-timing-critical for setup/hold relative to RD edge. |
| DVDD (17) | Digital Supply | +5V supply for logic outputs; tied to AVDD in most layouts to minimize supply separation. |
| SHDN (18) | Shutdown Control | Active-low enable; pulls IDD to 1.7mA and disables outputs/conversion until wake-up completes. |
| CONVST (19) | Conversion Start | Falling-edge triggered; initiates SAR cycle only if CS is LOW-prevents spurious conversions. |
| RD (20) | Read Strobe | Active-low data latch enable; controls output driver activation during parallel read cycles. |
| CS (21) | Chip Select | Active-low decoder input; gates CONVST and RD functionality-essential for multi-device bus sharing. |
| BUSY (22) | Conversion Status | Open-drain output LOW during conversion; used for polling or interrupt-driven data capture. |
| VSS (23) | Negative Supply | –5V for bipolar operation; tied to AGND for unipolar mode-defines input range polarity and reference headroom. |
| AVDD (24) | Analog Supply | +5V analog supply; bypassed with 10µF + 0.1µF to AGND to suppress supply-induced distortion. |
Key Features
| Feature | Design Value |
|---|---|
| Internal synchronized clock | Eliminates external clock source and associated jitter/noise coupling-simplifies layout and improves SNR. |
| Instant wake-up from shutdown | 350ns recovery enables power cycling between samples without throughput penalty-ideal for intermittent sensing. |
| Flexible unipolar/bipolar input modes | Single device supports both 0–5V sensor outputs and ±2.5V differential amplifier outputs-reduces BOM count. |
| Overdrivable VREF pin | Allows external reference (e.g., LT1019A-2.5) to improve tempco to 5ppm/°C-enhances long-term accuracy in industrial environments. |
| High-impedance analog input | ±1µA leakage and 25pF capacitance simplify front-end buffering-permits direct connection to low-output-impedance op amps like LT1360. |
Applications
| High-Speed Data Acquisition | Digital Signal Processing |
|---|---|
Use Scenario: Real-time waveform capture in oscilloscopes and automated test equipment with 300kHz analog bandwidth requirement. IC Role / Device Role / Timing Role: Primary sampling engine converting conditioned analog signals to 12-bit parallel data for FPGA preprocessing. Use Value: 600ksps rate and 70dB S/(N+D) ensure faithful digitization of fast transients without aliasing or quantization noise dominance. | Use Scenario: Front-end ADC in telecom baseband processing where 100kHz–300kHz IF signals require high dynamic range. IC Role / Device Role / Timing Role: High-fidelity analog interface feeding FFT engines in DSPs; uses BUSY/RD handshake for deterministic latency. Use Value: ±1LSB linearity and 78dB THD preserve signal integrity for modulation error ratio (MER) calculations in QAM demodulation. |
| Multiplexed Data Acquisition Systems | Audio and Telecom Processing |
Use Scenario: Channel-scanning in multichannel environmental monitoring systems with thermocouple/RTD inputs routed through analog multiplexer. IC Role / Device Role / Timing Role: Shared ADC resource per channel; SHDN pin powers down between scans to reduce average system power. Use Value: 8.5mW shutdown power and 350ns wake-up allow microsecond-scale channel switching without sacrificing throughput. | Use Scenario: Digitizing audio bandpass signals (20Hz–20kHz) in voice-over-IP gateways and spectrum analyzers. IC Role / Device Role / Timing Role: Precision sampling stage preceding digital filtering and compression algorithms; leverages internal reference for consistent gain. Use Value: 74dB S/(N+D) at Nyquist ensures >11.5 ENOB-meets ITU-T G.711 SNR requirements for telephony-grade audio. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 12-bit, 600ksps ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS7822U | 2.7V–5.25V single-supply only; SPI interface; 1MSPS max; no internal reference. | Requires external reference and serial interface logic; better suited for low-voltage, space-constrained designs. | Select when board area is limited and microcontroller has SPI but lacks parallel bus resources. |
| MAX11200EEE+ | 24-bit delta-sigma ADC; 1ksps max; internal oscillator; 114dB dynamic range. | Orders-of-magnitude higher resolution but 1000× slower-optimized for precision DC/low-frequency measurements, not speed. | Select for weigh scales or strain gauge readouts where resolution outweighs speed; not a functional replacement for LTC1279CG#PBF. |
Compared with ADS7822U and MAX11200EEE+, the LTC1279CG#PBF uniquely combines parallel interface simplicity, internal clocking, and 600ksps throughput with guaranteed ±1LSB linearity-making it optimal for real-time embedded systems needing deterministic latency and minimal external components.
Availability
LTC1279CG#PBF is available at Aetrix Electronics and suitable for high-speed data acquisition, digital signal processing, and multiplexed instrumentation systems requiring stable component supply and long-term manufacturability.
Supply support for LTC1279CG#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC1279CG#PBF belongs to ADI's legacy Linear Technology precision data acquisition product line, designed specifically for engineers building compact, low-power, high-accuracy sampling systems where ease of interface and guaranteed AC/DC specs are critical.
FAQ
What is the operating temperature range for the LTC1279CG#PBF?
The LTC1279CG#PBF is specified for commercial temperature operation from 0°C to 70°C. This grade is validated for use in office, laboratory, and non-extreme industrial environments. For extended-range applications, the LTC1279IG#PBF (–40°C to +85°C) is available. The LTC1279CG#PBF's performance parameters-including ±1LSB INL, 70dB S/(N+D), and 60mW power dissipation-are guaranteed across its full 0°C–70°C range.
Does the LTC1279CG#PBF require an external clock source?
No, the LTC1279CG#PBF does not require an external clock. It integrates a factory-trimmed internal clock that automatically synchronizes to each CONVST falling edge, delivering a fixed 1.4µs conversion time. This eliminates clock distribution noise, simplifies PCB layout, and removes timing skew concerns-key advantages over externally clocked ADCs. The internal clock is enabled by default and cannot be disabled.
How does the power shutdown feature work on the LTC1279CG#PBF?
The LTC1279CG#PBF enters low-power shutdown when the SHDN pin is driven LOW, reducing supply current to 1.7mA typical and disabling all analog and digital functions except the SHDN input receiver. Wake-up is instantaneous: a HIGH transition on SHDN triggers full functionality within 350ns, allowing the device to resume sampling without reinitialization. This enables precise power gating in battery-operated or energy-conscious systems.
Can the internal reference of the LTC1279CG#PBF be overdriven with an external reference?
Yes, the VREF pin (Pin 2) of the LTC1279CG#PBF can be overdriven with an external reference voltage ≥2.45V and ≤4.8V. Driving VREF externally overrides the internal 2.42V bandgap, enabling input span adjustment-for example, using an LT1019A-2.5 to achieve ±2.582V full-scale and improved 5ppm/°C tempco. The internal reference remains disconnected during overdrive, preventing conflict or damage.
What are the absolute maximum ratings for the analog input voltage on the LTC1279CG#PBF?
The absolute maximum analog input voltage for the LTC1279CG#PBF is –0.3V to VDD + 0.3V in unipolar mode (VDD = 5V), or VSS – 0.3V to VDD + 0.3V in bipolar mode (VSS = –5V, VDD = 5V). Exceeding these limits risks latch-up or parametric degradation. For reliable operation, the recommended input range is strictly 0V–5V (unipolar) or ±2.5V (bipolar), with clamping diodes protecting against brief overvoltage events up to ±80mA.
LTC1279CG#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 600k
- Number of Inputs:
- 1
- Input Type:
- Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V, -2.45V ~ 5.25
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 24-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1279CG#PBF FAQ
1.How can I place an order for LTC1279CG#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1279CG#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1279CG#PBF reliable?
The price and inventory of LTC1279CG#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1279CG#PBF is usually 5 days.
3.What payment methods are accepted for LTC1279CG#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1279CG#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1279CG#PBF?
LTC1279CG#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1279CG#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1279CG#PBF?
For technical support, including LTC1279CG#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1279CG#PBF requirements.
6.How does Aetrix verify that LTC1279CG#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1279CG#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1279CG#PBF meets industry standards.
7.What is the process for return or replacement of LTC1279CG#PBF?
All LTC1279CG#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1279CG#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1279CG#PBF part is unused and in its original packaging.
Return procedure for LTC1279CG#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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