Analog Devices Inc. LTC1279CSW#TRPBF
- Part No.:
- LTC1279CSW#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC1279CSW#TRPBF.pdf
- Description:
- IC ADC 12BIT SAR 24SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1279CSW#TRPBF from Analog Devices (formerly Linear Technology) is a 12-bit, 600ksps successive-approximation ADC with internal reference, synchronized clock, and power shutdown. It operates from single 5V or ±5V supplies, delivers 70dB S/(N+D) at 100kHz, consumes 60mW typical, and supports unipolar (0V–5V) or bipolar (±2.5V) input ranges - used in high-speed data acquisition systems interfacing to DSPs and FIFOs.
For engineers reviewing the LTC1279CSW#TRPBF datasheet, LTC1279CSW#TRPBF pinout, LTC1279CSW#TRPBF application, or LTC1279CSW#TRPBF equivalent, this page provides verified specifications, package mapping, functional interface details, and real-world timing and accuracy constraints for embedded signal acquisition designs.
Technical Context
The LTC1279CSW#TRPBF implements a 12-bit capacitive DAC-based successive approximation architecture with integrated 160ns sample-and-hold and factory-trimmed internal 2.42V bandgap reference. Its internal clock is synchronized to each CONVST falling edge, eliminating asynchronous clock feedthrough issues.
It features three-state parallel digital outputs (D11–D0), BUSY status flag, and flexible control logic supporting Mode 1/2 read protocols. Input leakage is ±1µA, analog input capacitance is 25pF in sample mode, and aperture jitter is <50ps - enabling accurate undersampling up to 5MHz full-power bandwidth.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonic transfer and full-scale code coverage for precision measurement. |
| Sampling Rate | 600ksps maximum - enables 300kHz Nyquist-limited signal capture with 1.66µs minimum throughput time. |
| S/(N + D) | 70dB at 100kHz input - corresponds to ~11.4 effective bits, sufficient for 10-bit ENOB at 300kHz. |
| THD | –78dB at 100kHz - indicates low harmonic distortion for clean spectral analysis in telecom/audio applications. |
| INL / DNL | ±1LSB integral and differential linearity - ensures <0.025% gain error and monotonicity across full scale. |
| Power Dissipation | 60mW typical at 600ksps; 8.5mW in shutdown - allows thermal management in dense PCB layouts without forced cooling. |
| Reference Output | 2.420V ±20mV, ±10ppm/°C tempco - stable enough to drive external circuitry up to 800µA without external buffering. |
Pinout & Package
24-pin SO Wide (SW) package, 0.300" wide body, gull-wing leads, RoHS-compliant. Thermal resistance θJA = 130°C/W. Requires separate analog/digital ground planes and local 10µF + 0.1µF bypassing at AVDD/VREF.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN (1) | Analog Input | High-impedance node accepting 0V–5V (unipolar) or ±2.5V (bipolar); 25pF input capacitance during sampling. |
| VREF (2) | Reference Output | 2.42V internal reference output; can be overdriven externally to adjust input span in bipolar mode. |
| AGND (3) | Analog Ground | Single-point analog return; must be isolated from DGND except at star point near device. |
| D11–D4 (4–11) | Data Outputs (MSB-first) | Three-state CMOS outputs; active when CS=RD=LOW; bus-compatible with 5V µPs and DSPs. |
| DGND (12) | Digital Ground | Digital return path; connected to AGND only at single point to minimize noise coupling. |
| D3–D0 (13–16) | Data Outputs (LSB) | Completes 12-bit parallel word; same timing and drive strength as D11–D4. |
| DVDD (17) | Digital Supply | +5V supply for digital core; tied to AVDD in most designs to simplify power routing. |
| SHDN (18) | Shutdown Control | Active-low input; reduces current to 1.7mA and power to 8.5mW with 350ns wake-up to conversion readiness. |
| CONVST (19) | Conversion Start | Falling-edge-triggered; initiates SAR cycle only when CS is LOW; minimum pulse width 40ns. |
| RD (20) | Read Strobe | Enables output drivers during Mode 2 read; requires setup relative to BUSY↑ per timing spec t7/t8. |
| CS (21) | Chip Select | Active-low enable for CONVST and RD recognition; must be asserted before CONVST edge. |
| BUSY (22) | Status Flag | Open-drain or CMOS output; LOW during conversion (1.4µs typ), HIGH when data is valid. |
| VSS (23) | Negative Supply | –5V for bipolar operation; tied to AGND for unipolar mode; bypass with 0.1µF ceramic. |
| AVDD (24) | Analog Supply | +5V analog supply; requires 10µF tantalum + 0.1µF ceramic bypass to AGND for AC performance. |
Key Features
| Feature | Design Value |
|---|---|
| Internal synchronized clock | Eliminates external clock routing and jitter sensitivity; auto-synchronizes to each CONVST edge. |
| Instant wake-up from shutdown | 350ns recovery to first valid conversion - enables dynamic power gating between samples in burst-mode systems. |
| Flexible unipolar/bipolar input range | Configurable via supply rails only - no mode pins or register writes required. |
| Overdrivable reference pin (VREF) | Allows external reference injection (≥2.45V) to calibrate full-scale span in bipolar applications. |
| High-impedance analog input | ±1µA leakage and 25pF capacitance enable direct connection to op-amps like LT1360 without buffer stages. |
| Parallel interface with BUSY handshake | Supports both Mode 1 (CS-controlled) and Mode 2 (RD-controlled) reads - simplifies integration with legacy µP buses. |
Applications
| High-Speed Data Acquisition | Digital Signal Processing |
|---|---|
Use Scenario: Real-time voltage monitoring of motor phase currents in industrial inverters sampled at ≥200ksps. IC Role / Device Role / Timing Role: Primary ADC capturing analog feedback signals; uses internal clock and BUSY handshake for deterministic µP read timing. Use Value: 600ksps rate and 70dB S/(N+D) ensure accurate reconstruction of 100kHz harmonics in PWM-driven systems. |
Use Scenario: Front-end digitization in telecom baseband receivers requiring low THD for QAM demodulation. IC Role / Device Role / Timing Role: Sampling IF or baseband analog signals prior to FPGA-based FFT processing; leverages three-state outputs for shared bus access. Use Value: –78dB THD at 100kHz and 5MHz full-power bandwidth support clean capture of multi-carrier OFDM waveforms. |
| Multiplexed Data Acquisition Systems | Audio and Telecom Processing |
Use Scenario: 16-channel sensor hub in test equipment where one LTC1279CSW#TRPBF serves multiple inputs via external multiplexer. IC Role / Device Role / Timing Role: Central ADC with fast acquisition (160ns) and instant wake-up - minimizes dead time between channel switches. Use Value: Low 1.7mA shutdown current and 350ns wake-up allow power cycling per channel, reducing average system power by >85%. |
Use Scenario: Digitizing audio line-level signals (±2.5V) in professional audio interfaces with DC-coupled inputs. IC Role / Device Role / Timing Role: Bipolar-mode ADC providing true signed representation for DSP algorithms; uses internal reference for consistent offset. Use Value: ±1LSB INL/DNL and 74dB THD at Nyquist ensure <0.025% total harmonic distortion in 20kHz audio band. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 12-bit, 600ksps ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7892BRZ-1 | Same 12-bit SAR architecture, 600ksps, but requires external reference and clock; no internal shutdown. | Requires additional reference IC and clock source; less board area efficient but offers wider supply range (±12V analog). | Select when external reference calibration or dual-supply flexibility outweighs integration benefits of LTC1279CSW#TRPBF. |
| MAX1166BCAP+ | 12-bit, 500ksps max; includes internal reference and shutdown, but lacks bipolar input support and has lower S/(N+D) (68dB). | Unipolar-only; suitable for cost-sensitive industrial sensors but not for audio or spectrum analysis requiring bipolar full-scale. | Select for unipolar-only systems where 500ksps and 68dB S/(N+D) meet requirements and footprint is constrained. |
Compared with AD7892BRZ-1 and MAX1166BCAP+, the LTC1279CSW#TRPBF uniquely integrates internal reference, synchronized clock, and bipolar/unipolar configurability in a single 24-pin SOIC - reducing BOM count and layout complexity while maintaining 70dB AC performance at full speed.
Availability
LTC1279CSW#TRPBF is available at Aetrix Electronics and suitable for high-speed data acquisition, digital signal processing, and multiplexed sensor systems requiring stable component supply, long-term manufacturability, and guaranteed parametric performance across temperature.
Supply support for LTC1279CSW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC1279CSW#TRPBF belongs to Linear Technology's legacy high-speed precision ADC family, designed specifically for applications demanding low power, high AC accuracy, and simplified digital interfacing in space-constrained embedded systems.
FAQ
What is the maximum sampling frequency supported by the LTC1279CSW#TRPBF?
The LTC1279CSW#TRPBF supports a maximum sampling frequency of 600ksps, with a typical conversion time of 1.4µs and minimum throughput time of 1.66µs. This allows reliable capture of input signals up to 300kHz (Nyquist limit) while maintaining specified AC performance including 70dB S/(N+D) at 100kHz.
Does the LTC1279CSW#TRPBF require an external clock source?
No, the LTC1279CSW#TRPBF does not require an external clock. It includes an internally trimmed clock synchronized to each CONVST falling edge, eliminating clock distribution noise and simplifying system design. External clocking is neither supported nor necessary for standard operation.
Can the LTC1279CSW#TRPBF operate in bipolar mode with a single 5V supply?
No, the LTC1279CSW#TRPBF requires dual supplies (±5V) for bipolar operation. Pin 23 (VSS) must be connected to –5V to enable ±2.5V input range. With only +5V applied to AVDD/DVDD and VSS tied to AGND, the device operates in unipolar mode (0V–5V input range).
What is the purpose of the SHDN pin on the LTC1279CSW#TRPBF?
The SHDN (shutdown) pin on the LTC1279CSW#TRPBF is an active-low control that reduces supply current to 1.7mA and power dissipation to 8.5mW. It supports instant wake-up - conversion can begin within 350ns after SHDN is deasserted - making it ideal for burst-mode or duty-cycled acquisition systems.
How is the reference voltage handled in the LTC1279CSW#TRPBF?
The LTC1279CSW#TRPBF includes a factory-trimmed 2.42V internal bandgap reference available at VREF (pin 2). It can drive up to 800µA and is used internally for the DAC. The pin may be overdriven with an external reference ≥2.45V to adjust full-scale range in bipolar applications, but driving below 2.45V is not recommended.
LTC1279CSW#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 600k
- Number of Inputs:
- 1
- Input Type:
- Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V, -2.45V ~ 5.25
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 24-SOIC
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1279CSW#TRPBF FAQ
1.How can I place an order for LTC1279CSW#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1279CSW#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1279CSW#TRPBF reliable?
The price and inventory of LTC1279CSW#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1279CSW#TRPBF is usually 5 days.
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Once your LTC1279CSW#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1279CSW#TRPBF?
For technical support, including LTC1279CSW#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1279CSW#TRPBF requirements.
6.How does Aetrix verify that LTC1279CSW#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC1279CSW#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1279CSW#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC1279CSW#TRPBF?
All LTC1279CSW#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1279CSW#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1279CSW#TRPBF part is unused and in its original packaging.
Return procedure for LTC1279CSW#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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