Analog Devices Inc. LTC1279ISW#PBF
- Part No.:
- LTC1279ISW#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC1279ISW#PBF.pdf
- Description:
- IC ADC 12BIT SAR 24SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1279ISW#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 600ksps successive-approximation ADC with internal reference, synchronized clock, and power shutdown. It operates from single 5V or ±5V supplies, delivers 70dB S/(N+D) at 100kHz, consumes 60mW typical, and supports unipolar (0V–5V) or bipolar (±2.5V) input ranges in industrial temperature range (–40°C to +85°C). It is used in high-speed data acquisition systems requiring low-power, self-contained conversion.
For engineers reviewing the LTC1279ISW#PBF datasheet, LTC1279ISW#PBF pinout, LTC1279ISW#PBF application, or LTC1279ISW#PBF equivalent, key selection considerations include guaranteed ±1LSB INL/DNL, 1.4µs conversion time with no external clock required, flexible parallel interface timing (Mode 2), and verified performance under industrial thermal stress.
Technical Context
The LTC1279ISW#PBF implements a 12-bit capacitive DAC-based successive approximation register (SAR) architecture with integrated sample-and-hold (160ns acquisition time) and factory-trimmed internal 2.42V bandgap reference. Its internal clock synchronizes automatically to each CONVST falling edge, eliminating asynchronous clock feedthrough issues.
It features three-state parallel digital outputs (D11–D0), active-low control signals (CS, RD, CONVST), and dedicated BUSY status output. Power management includes SHDN input enabling 8.5mW shutdown mode with 350ns wake-up latency - critical for burst-mode acquisition in DSP and telecom front-ends.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonic transfer and full-scale code coverage for precision measurement. |
| Sampling Rate | 600ksps maximum - enables real-time capture of signals up to 300kHz Nyquist bandwidth. |
| S/(N + D) | 70dB at 100kHz input - ensures ≥11.3 effective bits for dynamic signal fidelity in spectrum analysis. |
| INL / DNL | ±1LSB max - supports accurate DC calibration and linearity-critical applications like sensor digitization. |
| Conversion Time | 1.4µs typ - defines minimum throughput interval; combined with 160ns acquisition yields 1.66µs total cycle time. |
| Power Dissipation | 60mW typ at 600ksps; 8.5mW in shutdown - enables thermally constrained embedded designs without forced cooling. |
| Operating Temp | –40°C to +85°C - qualified for industrial environments including motor control and test equipment. |
Pinout & Package
Package: 24-lead plastic SO Wide (SW), 0.300" wide body, JEDEC MS-013AC compliant. Thermal resistance θJA = 130°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN (1) | Analog Input | High-impedance node accepting 0V–5V (unipolar) or ±2.5V (bipolar); requires <160ns settling after sampling transient. |
| VREF (2) | Reference Output | 2.42V ±20mV buffered output; drives up to 800µA; must be bypassed with 10µF tantalum + 0.1µF ceramic. |
| AGND (3) | Analog Ground | Single-point analog return; isolated from DGND to minimize digital noise coupling into conversion path. |
| D11–D4 (4–11) | Data Outputs (MSB-first) | Three-state parallel bus; D11 = MSB; enabled only when CS = LOW and RD = LOW. |
| DGND (12) | Digital Ground | Return for DVDD and digital I/O; connected to AGND at single point near pin 3 per layout guidelines. |
| D3–D0 (13–16) | Data Outputs (LSB) | Completes 12-bit word; D0 = LSB; same enable conditions as D11–D4. |
| DVDD (17) | Digital Supply | +5V supply for logic outputs; tied directly to AVDD to minimize supply differential. |
| SHDN (18) | Shutdown Control | Active-low input; pulls IDD to 1.7mA typ; wake-up latency ≤350ns to first valid CONVST response. |
| CONVST (19) | Conversion Start | Falling-edge triggered; initiates SAR cycle only if CS = LOW; timing-critical for Mode 1/2 interface. |
| RD (20) | Read Strobe | Active-low; enables output drivers during BUSY = LOW; defines t8 access window for latch capture. |
| CS (21) | Chip Select | Active-low enable for CONVST and RD recognition; must be stable before t2 setup time (20ns min). |
| BUSY (22) | Status Output | Open-drain active-low flag; goes LOW at CONVST↓ and HIGH after conversion complete (t5 delay). |
| VSS (23) | Negative Supply | –5V for bipolar operation; tied to AGND for unipolar; bypassed with 0.1µF ceramic close to pin. |
| AVDD (24) | Analog Supply | +5V analog supply; bypassed with 10µF tantalum + 0.1µF ceramic; shares net with DVDD. |
Key Features
| Feature | Design Value |
|---|---|
| Internal synchronized clock | Eliminates need for external clock source or timing alignment - reduces BOM count and layout complexity. |
| Flexible parallel interface (Mode 2) | Supports microprocessor handshaking with RD/BUSY timing; avoids bus contention in shared-data environments. |
| Instant wake-up from shutdown | 350ns latency enables power gating between samples - critical for battery-powered portable instruments. |
| Overdrivable VREF pin | Accepts external 2.45V–4.8V reference to adjust input span - enables calibrated bipolar full-scale tuning. |
| High-impedance analog input | 25pF input capacitance in sample mode; ±1µA leakage - simplifies driver selection (e.g., LT1360, LT1220). |
Applications
| High-Speed Data Acquisition | Digital Signal Processing Front-End |
|---|---|
Use Scenario: Real-time voltage monitoring in automated test equipment capturing transient waveforms at 600ksps. IC Role / Device Role / Timing Role: Primary sampling ADC interfacing directly to FIFO buffer; provides 12-bit parallel output synchronized to system clock via BUSY handshake. Use Value: Guaranteed ±1LSB linearity and 70dB S/(N+D) ensure measurement repeatability across temperature; 1.4µs conversion enables tight trigger-to-capture latency. |
Use Scenario: Digitizing analog sensor outputs (e.g., vibration, current) for FFT-based spectral analysis in industrial condition monitoring. IC Role / Device Role / Timing Role: High-fidelity front-end converter feeding fixed-point DSP; uses internal reference and no external clock to reduce jitter-sensitive paths. Use Value: Full-power bandwidth of 5MHz and 500kHz full-linear bandwidth support undersampling of RF-modulated sensor signals without aliasing degradation. |
| Multiplexed Sensor Systems | Audio and Telecom Signal Chain |
Use Scenario: Multi-channel environmental monitoring (temperature, pressure, humidity) using analog multiplexer switching between sensors. IC Role / Device Role / Timing Role: Shared ADC resource with fast wake-up (350ns) and low 8.5mW shutdown power - minimizes idle energy per channel. Use Value: Unipolar/bipolar mode flexibility allows direct connection to both ratiometric and offset sensors without external level-shifting circuitry. |
Use Scenario: Baseband digitization in voice-band telecom interfaces (e.g., PCM codec front-end, echo canceller input). IC Role / Device Role / Timing Role: Low-noise, low-distortion ADC operating at 600ksps with THD ≤ –78dB at 100kHz - meets ITU-T G.712 requirements. Use Value: 74dB THD at Nyquist and spurious-free dynamic range >70dB preserve signal integrity for real-time voice processing algorithms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 12-bit, 600ksps SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS7800U | 12-bit, 1.25Msps, ±5V supply, no internal reference - requires external REF200 or similar; higher power (120mW). | Higher speed but lacks integrated clock and shutdown; needs more board space and design effort for reference/bypassing. | Choose when throughput >600ksps is mandatory and system already provides precision reference. |
| MAX1166BCPP | 12-bit, 250ksps, +5V only, internal reference, SPI interface - slower, serial-only, no bipolar mode. | Compact solution for space-constrained microcontroller-based systems where parallel bus is unavailable. | Choose for cost-sensitive, lower-speed embedded control where SPI simplifies routing and reduces pin count. |
Compared with ADS7800U and MAX1166BCPP, the LTC1279ISW#PBF uniquely combines 600ksps speed, internal reference, bipolar/unipolar flexibility, and instant-wake shutdown - making it optimal for industrial DAQ where integration, thermal robustness, and interface simplicity are prioritized over raw speed or serial footprint.
Availability
LTC1279ISW#PBF is available at Aetrix Electronics and suitable for high-speed data acquisition, digital signal processing front-ends, and multiplexed sensor systems requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for LTC1279ISW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC1279ISW#PBF belongs to ADI's legacy Linear Technology precision data acquisition product line, designed specifically for industrial-grade, self-contained, low-power SAR ADC applications demanding guaranteed AC/DC specifications over temperature.
FAQ
What is the operating temperature range for the LTC1279ISW#PBF?
The LTC1279ISW#PBF is rated for industrial operation from –40°C to +85°C. This is confirmed by the "I" grade suffix in the part number and validated in the Absolute Maximum Ratings table (page 2) and Operating Temperature Range specification (page 2) of the official datasheet. The device maintains ±1LSB INL/DNL and 70dB S/(N+D) across this full range.
Does the LTC1279ISW#PBF require an external clock?
No, the LTC1279ISW#PBF does not require an external clock. It contains an internally trimmed clock that automatically synchronizes to each falling edge of the CONVST signal. This eliminates clock distribution noise and simplifies system timing - a key differentiator versus competitive SAR ADCs requiring precise external clock sources.
Can the LTC1279ISW#PBF operate in both unipolar and bipolar modes?
Yes, the LTC1279ISW#PBF supports both modes: unipolar (0V to 5V input with single +5V supply) and bipolar (±2.5V input with ±5V supplies). Mode selection is determined by VSS connection - tied to AGND for unipolar, –5V for bipolar - as specified in the Applications Information section (page 11) and Absolute Maximum Ratings (page 2).
What is the typical power consumption of the LTC1279ISW#PBF during active conversion?
The LTC1279ISW#PBF draws 12mA to 24mA from AVDD/DVDD (typical 12mA) and 0.12mA to 0.30mA from VSS at 600ksps, resulting in 60mW typical power dissipation. This value is measured under standard conditions (AVDD = DVDD = 5V, VSS = –5V, fSAMPLE = 600kHz) and appears in the Power Requirements table (page 4) of the datasheet.
How is the reference voltage handled on the LTC1279ISW#PBF?
The LTC1279ISW#PBF integrates a factory-trimmed 2.42V bandgap reference, accessible at VREF (pin 2). It can drive up to 800µA and must be bypassed with 10µF tantalum + 0.1µF ceramic. The VREF pin is also overdrivable (2.45V–4.8V) to adjust input span - a feature documented in the Applications Information section (pages 11–12) for calibrated bipolar operation.
LTC1279ISW#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 600k
- Number of Inputs:
- 1
- Input Type:
- Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V, -2.45V ~ 5.25
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 24-SOIC
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1279ISW#PBF FAQ
1.How can I place an order for LTC1279ISW#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1279ISW#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1279ISW#PBF reliable?
The price and inventory of LTC1279ISW#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1279ISW#PBF is usually 5 days.
3.What payment methods are accepted for LTC1279ISW#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1279ISW#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1279ISW#PBF?
LTC1279ISW#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1279ISW#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1279ISW#PBF?
For technical support, including LTC1279ISW#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1279ISW#PBF requirements.
6.How does Aetrix verify that LTC1279ISW#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1279ISW#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1279ISW#PBF meets industry standards.
7.What is the process for return or replacement of LTC1279ISW#PBF?
All LTC1279ISW#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1279ISW#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1279ISW#PBF part is unused and in its original packaging.
Return procedure for LTC1279ISW#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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