Analog Devices Inc. LTC1403CMSE-1#PBF

Overview

LTC1403CMSE-1#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 2.8 Msps serial analog-to-digital converter with differential inputs, 3V single-supply operation, ±1.25V bipolar input range, and integrated 2.5V bandgap reference. It delivers 70.5 dB SINAD at 100 kHz and supports high-speed portable data acquisition in space-constrained systems.

For engineers reviewing the LTC1403CMSE-1#PBF datasheet, LTC1403CMSE-1#PBF pinout, LTC1403CMSE-1#PBF application, or LTC1403CMSE-1#PBF equivalent, key selection criteria include its 39 ns acquisition time, 80 dB CMRR at 1 MHz, 10 µW sleep-mode power, 10-lead MSOP package, and compatibility with standard 3-wire SPI-like serial interfaces.

Technical Context

The LTC1403CMSE-1#PBF implements a fully differential sample-and-hold front-end followed by a 12-bit successive-approximation ADC core. Its timing logic synchronizes conversion start (CONV↑) with a 16-cycle serial output window aligned to SCK rising edges, enabling deterministic 2.8 Msps throughput with a 50.4 MHz clock.

It features dual shutdown modes: Nap mode (3 mW, 1.1 mA) and Sleep mode (10 µW, 2 µA), both entered via CONV pulse sequences. The internal 2.5V reference exhibits ±15 ppm/°C tempco and settles in 2 ms after wake-up, while the analog inputs tolerate 0 V to VDD common-mode voltage with ±1.25 V differential swing.

Key Specifications

Pinout & Package

Package: 10-lead plastic MSOP (MSE), exposed pad (Pin 11) must be soldered to PCB ground plane per θ_JA = 40°C/W thermal spec.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Compared with ADS8326IDRCT and MAX1190ETE+, the LTC1403CMSE-1#PBF uniquely balances 12-bit accuracy, 2.8 Msps speed, integrated reference, and ultra-low-power sleep mode in a 3mm × 3mm MSOP - making it optimal for portable, battery-sensitive, space-constrained signal acquisition where full 16-bit resolution is unnecessary.

Availability

LTC1403CMSE-1#PBF is available at Aetrix Electronics and suitable for communications receiver front-ends, industrial data acquisition systems, and uninterruptible power supply monitoring requiring stable component supply and long-term obsolescence management.

Supply support for LTC1403CMSE-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its high-performance analog portfolio, emphasizing precision signal conditioning, power management, and data conversion for demanding industrial and communications applications.

The LTC1403CMSE-1#PBF belongs to Linear's legacy high-speed SAR ADC family, designed specifically for portable, low-power, high-fidelity digitization in space-constrained systems where differential noise immunity and fast throughput are essential.

FAQ

What is the guaranteed operating temperature range for the LTC1403CMSE-1#PBF?

The LTC1403CMSE-1#PBF is rated for 0°C to 70°C ambient operation, as confirmed by its "C" grade designation in the ordering information table. All electrical specifications-including INL, offset error, and SINAD-are guaranteed over this full industrial temperature range, not just at 25°C.

Does the LTC1403CMSE-1#PBF require an external reference, or can it operate with only the internal 2.5V reference?

The LTC1403CMSE-1#PBF operates fully with its internal 2.5V bandgap reference; no external reference is required. The VREF pin (Pin 3) must be bypassed with a 10 µF ceramic capacitor to ground. An external reference (2.55V to VDD) may optionally overdrive VREF for improved accuracy or different input spans.

How does the LTC1403CMSE-1#PBF enter Sleep mode, and what is the wake-up latency?

The LTC1403CMSE-1#PBF enters Sleep mode by applying four or more CONV pulses while SCK is held static (high or low). Wake-up latency is defined by VREF settling time: 2 ms after the first SCK edge post-wake, as specified in Note 14 and the Internal Reference Characteristics table.

What is the absolute maximum analog input voltage range for AIN+ and AIN– on the LTC1403CMSE-1#PBF?

Per Absolute Maximum Ratings, AIN+ and AIN– each tolerate –0.3 V to (VDD + 0.3 V). With VDD = 3 V, this is –0.3 V to 3.3 V. However, functional differential input range remains ±1.25 V (i.e., AIN+ – AIN– ∈ [–1.25 V, +1.25 V]), and common-mode voltage must stay within 0 V to VDD.

Is the LTC1403CMSE-1#PBF pin-compatible with the LTC1403A-1 series variants?

No - the LTC1403CMSE-1#PBF is a 12-bit device (LTC1403-1 family), while LTC1403ACMSE-1#PBF is its 14-bit counterpart (LTC1403A-1 family). They share identical pinout, package, and interface timing, but differ in resolution, INL/DNL specs, and dynamic performance (e.g., SINAD is 70.5 dB vs. 73.5 dB at 100 kHz).