Analog Devices Inc. LTC1405IGN#PBF

Overview

LTC1405IGN#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 5Msps pipelined analog-to-digital converter with integrated sample-and-hold, programmable gain amplifier (PGA), and on-chip 4.096V/2.048V reference. It operates from single 5V or dual ±5V supplies, delivers 71.3dB S/(N+D) at 2.5MHz input, and supports rail-to-rail differential inputs with 75dB CMRR for high-precision data acquisition in telecom and DSP systems.

For engineers reviewing the LTC1405IGN#PBF datasheet, LTC1405IGN#PBF pinout, LTC1405IGN#PBF application, or LTC1405IGN#PBF equivalent, key selection criteria include its 100MHz full-power bandwidth, ±0.35LSB INL over temperature, flexible ±2.048V/±1.024V/±0.512V input ranges, 28-pin SSOP package, and OVDD-supported 3V/5V logic interfacing - all critical for high-speed, low-noise signal digitization.

Technical Context

The LTC1405IGN#PBF implements a 12-bit pipelined CMOS ADC architecture with a dedicated differential input sample-and-hold stage capable of acquiring signals up to 100MHz. Its digital correction logic ensures no missing codes and enables two's complement parallel output with overflow flag (OF).

It integrates a factory-trimmed 2.5V bandgap reference (VCM), selectable internal reference (4.096V or 2.048V via SENSE pin), and a digitally controlled PGA offering 1× or 2× gain. The separate OVDD supply allows direct interface to 3V or 5V logic without level shifters, while GND and OGND separation maintains analog/digital noise isolation.

Key Specifications

Pinout & Package

Package: 28-lead narrow-body SSOP (GN package), 5.6mm × 10.2mm, 0.635mm pitch, RoHS-compliant, lead-free (Pb-free) finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9220ARZ and LTC2245IUP#PBF, the LTC1405IGN#PBF uniquely combines integrated PGA, on-chip reference, and SSOP packaging - reducing BOM count and layout risk for medium-speed, mixed-signal embedded systems where ease of use and analog integration outweigh raw speed or resolution.

Availability

LTC1405IGN#PBF is available at Aetrix Electronics and suitable for telecommunications baseband processing, digital signal processing acceleration, and multiplexed data acquisition systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for LTC1405IGN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC1405IGN#PBF belongs to Linear Technology's legacy high-speed precision ADC product line, designed specifically for applications demanding low power, integrated analog front-end functionality, and robust performance across temperature in space- and cost-constrained systems.

FAQ

What supply configurations does the LTC1405IGN#PBF support?

The LTC1405IGN#PBF operates from either a single 5V supply (VSS = 0V) or dual ±5V supplies (VSS = –5V). Both configurations are fully supported with identical AC/DC specifications. The VCM pin provides a 2.5V bias for single-supply operation, and the SENSE pin selects internal reference voltage (4.096V or 2.048V) regardless of supply mode. Decoupling requirements differ slightly: dual supply requires 1µF ceramics on both VDD and VSS, while single supply needs only VDD bypassing.

How does the GAIN pin affect input range and noise performance in the LTC1405IGN#PBF?

The GAIN pin on the LTC1405IGN#PBF selects 1× or 2× programmable gain for the input PGA: 5V = 1×, 0V = 2×. When GAIN = 2×, the effective input range halves (e.g., ±2.048V becomes ±1.024V), but input-referred noise remains constant, improving effective number of bits (ENOB) for small signals. Measured input-referred noise is 0.22 LSBRMS at ±2.048V range and 0.33 LSBRMS at ±1.024V/2× mode - confirming that PGA gain amplifies both signal and noise equally, preserving SNR.

What is the purpose of the OF (overflow) pin on the LTC1405IGN#PBF, and how is it used?

The OF (overflow) pin on the LTC1405IGN#PBF is an active-high indicator that signals when the analog input exceeds the selected full-scale range. It asserts high when the digital output equals 011111111111 (positive overflow) or 100000000000 (negative overflow). This flag enables real-time clipping detection in firmware without parsing all 12 data bits, allowing immediate gain adjustment or alarm triggering. Unlike comparator-based solutions, OF is synchronized to the ADC's internal timing and immune to metastability.

Can the LTC1405IGN#PBF interface directly with a 3.3V FPGA I/O bank?

Yes, the LTC1405IGN#PBF can interface directly with a 3.3V FPGA I/O bank by connecting OVDD to 3.3V and tying OGND to the FPGA's ground. The output drivers are specified down to 2.7V OVDD, with VOH ≥ 2.3V and VOL ≤ 0.4V at 1.6mA sink current - meeting 3.3V LVTTL/LVCMOS voltage thresholds. No series resistors or level translators are needed, provided the FPGA I/O is configured for 3.3V tolerant inputs and output loading stays below 30pF per pin.

What is the minimum clock frequency required for stable operation of the LTC1405IGN#PBF?

The LTC1405IGN#PBF requires a minimum clock frequency of 20kHz to maintain accurate conversion results. Below this rate, charge stored on internal pipeline capacitors may droop, causing gain and offset drift. However, the part includes an internal timer that refreshes dynamic logic if the clock is halted for ≥1ms - enabling ultra-low-power sleep modes. For continuous operation, f_SAMPLE must remain ≥20kHz; typical use cases operate at 1–5MHz, with t_H/t_L ≥20ns each.