Analog Devices Inc. LTC1406CGN#TRPBF

Overview

LTC1406CGN#TRPBF from Analog Devices (formerly Linear Technology) is a low-power, 8-bit, 20 Msps sampling analog-to-digital converter with differential input architecture, ±1 V full-scale range, ±1 LSB INL/DNL over temperature, and 250 MHz input bandwidth. It operates from a single 5 V supply, dissipates only 150 mW, and supports high-speed undersampling in RF and communications signal chains.

For engineers reviewing the LTC1406CGN#TRPBF datasheet, LTC1406CGN#TRPBF pinout, LTC1406CGN#TRPBF application, or LTC1406CGN#TRPBF equivalent, key selection criteria include its 20 Msps throughput with 5-cycle pipeline latency, rail-to-rail analog input common-mode range (0 V to VDD), separate OVDD/OGND for 3 V digital interfacing, and 60 dB CMRR up to 100 MHz - critical for noise-immune baseband and IF sampling.

Technical Context

The LTC1406CGN#TRPBF implements a 5-stage pipelined ADC architecture with an integrated 250 MHz differential sample-and-hold amplifier. Its track-and-hold acquires signals on CLK high and samples on the falling edge, delivering output data five clock cycles later.

It accepts true differential inputs (±1 V span) or single-ended configurations (2 V span referenced to VREF), with analog inputs tolerant from GND to VDD and common-mode rejection maintained at 60 dB up to 100 MHz. Power-down mode reduces supply current to 1 µA via SHDN pin.

Key Specifications

Pinout & Package

Package: 24-lead narrow SSOP (GN), RoHS-compliant, body size 7.6 mm × 4.9 mm, 0.635 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, low-power ADC applications.

Compared with AD9203ARUZ and MAX1186ETL+, the LTC1406CGN#TRPBF uniquely combines 5 V analog operation, true differential inputs with 60 dB CMRR, separate OVDD for 3 V logic interfacing, and 1 µA shutdown - making it optimal for hybrid-voltage, noise-sensitive, and power-gated systems.

Availability

LTC1406CGN#TRPBF is available at Aetrix Electronics and suitable for wireless infrastructure, digital video capture, high-speed test equipment, and CCD imaging systems requiring stable component supply and long-term production continuity.

Supply support for LTC1406CGN#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and DSP technologies for precision and high-speed applications.

The LTC1406CGN#TRPBF belongs to Linear's legacy high-speed ADC product line, designed specifically for low-power, wide-input-bandwidth digitization in communications, instrumentation, and imaging - emphasizing ease of use, noise immunity, and flexible voltage domain isolation.

FAQ

What is the operating temperature range for the LTC1406CGN#TRPBF?

The LTC1406CGN#TRPBF is specified for the commercial temperature range of 0°C to 70°C. Its DC accuracy parameters - including ±1 LSB integral nonlinearity (INL) and differential nonlinearity (DNL) - are guaranteed across this full range, ensuring consistent performance in office, lab, and indoor industrial environments without thermal calibration.

Does the LTC1406CGN#TRPBF support single-ended input operation?

Yes, the LTC1406CGN#TRPBF supports single-ended operation: tie AIN– to a fixed DC voltage (e.g., VREF = 2.5 V), then drive AIN+ with a ±1 V bipolar signal centered at that voltage. The device converts the difference [(AIN+) – (AIN–)], so a 2 V single-ended span is achieved - confirmed in the datasheet's "Analog Inputs" section and Figure 8a.

What is the purpose of the OF/UF pin on the LTC1406CGN#TRPBF?

The OF/UF (Overflow/Underflow) pin on the LTC1406CGN#TRPBF is a status flag indicating out-of-range conditions: logic high with D7–D0 = 11111111 signifies overrange (input > +1 V differential), while logic high with D7–D0 = 00000000 indicates underrange (input < –1 V differential). This enables real-time clipping detection without additional logic.

Can the LTC1406CGN#TRPBF interface directly with 3 V FPGA I/O banks?

Yes, the LTC1406CGN#TRPBF can interface directly with 3 V FPGA I/O banks using its dedicated OVDD and OGND pins. Set OVDD = 3.3 V and connect OGND to the FPGA's I/O ground. The D7–D0 and OF/UF outputs swing between OVDD and OGND, meeting 3 V logic thresholds - a key design feature explicitly documented in the "Digital Inputs and Outputs" section.

What is the minimum clock duty cycle required for full 20 Msps operation of the LTC1406CGN#TRPBF?

For reliable 20 Msps operation, the LTC1406CGN#TRPBF requires a clock duty cycle within 45%–55%, with each high and low phase ≥25 ns. Deviation beyond this range degrades interstage settling and increases DNL - as validated in Figure 11 (F11) of the datasheet, where DNL exceeds ±1 LSB outside 48%–52% duty cycle at 20 Msps.