Analog Devices Inc. LTC1409CSW#PBF

Overview

LTC1409CSW#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 800ksps successive-approximation ADC with differential analog inputs, ±2.5V bipolar input range, 72.5dB S/(N+D) at 400kHz, and dual shutdown modes (4mW Nap, 10µW Sleep). It integrates a precision 2.5V reference, 20MHz full-power bandwidth sample-and-hold, and µP-compatible 12-bit parallel output - used in high-speed data acquisition systems requiring low-latency, no-pipeline-delay conversion.

For engineers reviewing the LTC1409CSW#PBF datasheet, LTC1409CSW#PBF pinout, LTC1409CSW#PBF application, or LTC1409CSW#PBF equivalent, key selection criteria include its true differential input architecture with 60dB CMRR, ±1LSB INL/DNL over temperature, 900–1250ns conversion time, and separate CONVST/BUSY/CS/RD control for FIFO and DSP interfacing.

Technical Context

The LTC1409CSW#PBF employs a capacitive DAC-based successive approximation register (SAR) architecture with internal clock and zeroing switches for comparator offset nulling. Its differential sample-and-hold acquires signals within 150ns and supports both single-ended (–AIN grounded) and fully differential input configurations up to 20MHz bandwidth.

Conversion is initiated by a falling edge on CONVST while CS is low; BUSY goes low during conversion and rises when 12-bit data is latched and valid. The device features separate AVDD (5V analog), VSS (–5V analog), and OVDD (3V/5V digital output supply) rails, enabling direct interface to mixed-voltage logic without level shifters.

Key Specifications

Pinout & Package

Package: 28-lead plastic SO Wide (SW), RoHS-compliant, 0.300" wide body, θ_JA = 130°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Compared with ADS8325IPW and MAX1166ECM+, the LTC1409CSW#PBF uniquely balances 800ksps throughput, 72.5dB SINAD, true differential inputs, and dual shutdown - making it optimal for real-time, noise-immune acquisition where latency and bandwidth are design-critical.

Availability

LTC1409CSW#PBF is available at Aetrix Electronics and suitable for telecommunications baseband processing, digital signal processing front-ends, and multiplexed industrial data acquisition requiring stable component supply and long-term manufacturability.

Supply support for LTC1409CSW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LTC1409CSW#PBF belongs to ADI's legacy Linear Technology precision data converter family, engineered for high-speed, low-distortion sampling in demanding signal chain applications where timing determinism and noise immunity are essential.

FAQ

What is the maximum sampling rate supported by the LTC1409CSW#PBF?

The LTC1409CSW#PBF supports a maximum sampling rate of 800ksps, corresponding to a Nyquist frequency of 400kHz. This is guaranteed across the full operating temperature range (0°C to 70°C for the 'C' grade) with all AC specifications met, including 72.5dB S/(N+D) at 400kHz input. Conversion time is 900–1250ns, and minimum inter-conversion delay is 40ns.

Does the LTC1409CSW#PBF require an external reference, or does it have an internal one?

The LTC1409CSW#PBF includes an internal, factory-trimmed 2.500V bandgap reference with ±15ppm/°C tempco, accessible at the VREF pin. It can operate with this internal reference or accept an external reference applied to VREF. The REFCOMP pin must be bypassed with ≥1µF to AGND for stability. No external reference is required for basic operation.

How does the differential input architecture of the LTC1409CSW#PBF improve noise immunity?

The LTC1409CSW#PBF's differential input architecture provides 60dB common-mode rejection ratio (CMRR) up to 100kHz, allowing it to reject ground loops, power supply ripple, and EMI that appear equally on +AIN and –AIN. This enables accurate measurement of small differential signals in electrically noisy environments like motor drives or telecom line cards without additional filtering.

What are the power consumption characteristics of the LTC1409CSW#PBF in shutdown modes?

The LTC1409CSW#PBF offers two shutdown modes: Nap mode draws 0.8–1.2mA (≈4mW) and enables wake-up in 200ns; Sleep mode draws just 1µA (≈0.01mW) but requires longer wake-up. Both are selected via the NAP/SLP pin and activated by pulling SHDN low. Total active power is 80mW typical at ±5V supplies and 800ksps.

Can the LTC1409CSW#PBF interface directly with 3V logic systems?

Yes, the LTC1409CSW#PBF can interface directly with 3V logic. Its digital outputs are driven by a separate OVDD supply pin (Pin 27); connecting OVDD to a 3V rail configures the output drivers for 3V logic levels. VOH is ≥4.0V at 200µA sink (for 5V OVDD) and scales accordingly - no external level shifters are needed when OVDD = 3V.