Analog Devices Inc. LTC1409ISW#PBF
- Part No.:
- LTC1409ISW#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC1409ISW#PBF.pdf
- Description:
- IC ADC 12BIT SAR 28SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1409ISW#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 800ksps successive-approximation ADC with true differential inputs, ±2.5V bipolar input range, 72.5dB S/(N+D) at 400kHz, and integrated 2.5V reference. It operates from ±5V supplies, draws 80mW, and targets high-speed data acquisition in DSP and telecom systems.
For engineers reviewing the LTC1409ISW#PBF datasheet, LTC1409ISW#PBF pinout, LTC1409ISW#PBF application, or LTC1409ISW#PBF equivalent, key selection factors include its 20MHz full-power bandwidth, no-pipeline-delay parallel output, Nap/Sleep shutdown modes (4mW / 10µW), and differential common-mode rejection up to 60dB - all critical for noise-sensitive sampling in spectrum analysis and imaging.
Technical Context
The LTC1409ISW#PBF implements a capacitor-based SAR architecture with an internal sample-and-hold that acquires signals within 150ns and supports simultaneous differential sampling at up to 20MHz bandwidth. Its comparator offset is nulled via zeroing switches during acquisition, and conversion completes in 900–1250ns with no pipeline latency.
It features dual digital supply domains: AVDD/DGND for core logic and OVDD/OGND for 3V- or 5V-compatible output drivers. The VREF (2.500V ±20mV) and REFCOMP (4.06V) pins support internal reference operation or external overdrive, with 15ppm/°C tempco and 0.01 LSB/V line regulation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonic transfer function for precision measurement. |
| Sampling Rate | 800ksps maximum - enables Nyquist-limited 400kHz signal capture without aliasing in baseband applications. |
| S/(N + D) | 72.5dB at 400kHz input - corresponds to ~11.8 effective bits, suitable for medium-dynamic-range instrumentation. |
| INL / DNL | ±1LSB max over temperature - ensures <0.025% full-scale linearity error for calibrated sensor interfaces. |
| Input Range | ±2.5V differential - allows direct connection to op-amp outputs without level-shifting circuitry. |
| Power Modes | Nap (4mW) and Sleep (10µW) - reduces system idle power by >99% while retaining fast wake-up capability. |
| Common-Mode Rejection | 60dB up to 100kHz - suppresses ground-loop noise and EMI in industrial sensor front-ends. |
Pinout & Package
Package: 28-pin SO Wide (SW), 0.300" body width, RoHS-compliant lead-free (PbF).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| +AIN (1) | Differential analog input positive | Accepts signal up to AVDD; sampled simultaneously with –AIN for true differential acquisition. |
| –AIN (2) | Differential analog input negative | Enables common-mode noise rejection; voltage must stay within AVDD/VSS rails. |
| VREF (3) | 2.50V reference output | Factory-trimmed bandgap source; can be overdriven externally to adjust full-scale range. |
| REFCOMP (4) | Reference amplifier compensation | Requires ≥1µF bypass to AGND; stabilizes internal reference amplifier loop. |
| AGND (5) | Analog ground reference | Must be tied to DGND and OVDD ground; star-point for analog decoupling. |
| D11–D0 (6–13,15–18) | 12-bit parallel data outputs | Three-state CMOS outputs; driven only when CS low and RD active. |
| BUSY (25) | Conversion status indicator | Active-low open-drain signal; rising edge marks valid data ready for read. |
| CONVST (23) | Conversion start trigger | Falling-edge sensitive; initiates SAR cycle and resets register; timing-critical for throughput. |
| SHDN / NAP/SLP (21,20) | Power management control | NAP/SLP selects mode; SHDN asserts shutdown - enables two-tier low-power sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| True differential input architecture | Rejects common-mode noise up to 60dB while preserving signal integrity across 20MHz bandwidth. |
| No pipeline delay | Delivers first valid conversion result within one clock cycle - essential for real-time closed-loop control. |
| Separate OVDD supply for outputs | Allows direct interfacing to 3V microcontrollers without level shifters or bus contention risks. |
| Internal 2.5V reference with 15ppm/°C drift | Eliminates external reference component count while maintaining ±1LSB INL over –40°C to 85°C. |
| Two-stage power shutdown (Nap/Sleep) | Reduces quiescent current from 9mA to 1µA - extends battery life in portable data loggers. |
Applications
| Telecommunications Baseband Sampling | Digital Signal Processing Front-End |
|---|---|
Use Scenario: Digitizing IF signals in cellular basestation receivers before FPGA-based demodulation. IC Role / Device Role / Timing Role: High-fidelity 12-bit sampling ADC with 20MHz analog bandwidth and precise timing alignment via BUSY/CONVST handshake. Use Value: 72.5dB SINAD at 400kHz preserves adjacent-channel interference margin; differential inputs reject PCB-level coupling from RF sections. | Use Scenario: Capturing sensor waveforms in real-time vibration analysis systems using TI C6000 DSPs. IC Role / Device Role / Timing Role: Low-latency parallel-output ADC synchronized to DSP external memory interface with no pipeline stall. Use Value: Nap-mode power gating cuts standby consumption to 4mW, enabling always-on monitoring without thermal derating. |
| Multiplexed Data Acquisition Systems | Imaging System Digitization |
Use Scenario: Channel-scanning in 16-channel medical EEG amplifiers requiring <±1LSB integral linearity per channel. IC Role / Device Role / Timing Role: Precision SAR ADC with ±1LSB INL/DNL over temperature, driven by multiplexer with <150ns settling time. Use Value: Bipolar ±2.5V input range matches typical bio-amplifier output swing, eliminating DC-blocking capacitors and associated phase distortion. | Use Scenario: Converting analog video outputs from CCD line sensors in industrial inspection cameras. IC Role / Device Role / Timing Role: High-throughput ADC with 800ksps rate and 900ns conversion time, triggered by pixel clock edge. Use Value: Full-power bandwidth of 15MHz supports sharp-edged line transitions without slew-induced distortion in monochrome imaging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 12-bit, high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8325IPW | 16-bit resolution, 100ksps max, SPI interface, single-ended input only | Better DC accuracy but lower speed; lacks differential input and shutdown flexibility | Choose for high-precision, low-throughput sensor logging where resolution > speed. |
| MAX1166ECM+ | 12-bit, 500ksps, internal reference, SPI interface, 20-pin TSSOP | Lower power (15mW), smaller package, but no Nap/Sleep modes or 20MHz bandwidth | Choose for space-constrained embedded systems needing moderate speed and minimal BOM count. |
Compared with ADS8325IPW and MAX1166ECM+, the LTC1409ISW#PBF uniquely balances 800ksps throughput, true differential input, and dual-stage shutdown - making it optimal for battery-powered spectrum analyzers and real-time DSP front-ends where latency, noise immunity, and dynamic power scaling are co-critical.
Availability
LTC1409ISW#PBF is available at Aetrix Electronics and suitable for telecommunications infrastructure, digital signal processing hardware, and high-speed data acquisition systems requiring stable component supply across industrial temperature ranges (–40°C to 85°C).
Supply support for LTC1409ISW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC1409ISW#PBF belongs to ADI's legacy Linear Technology precision data converter portfolio, designed specifically for high-speed, low-distortion sampling in noise-critical instrumentation and real-time signal processing applications.
FAQ
What is the operating temperature range for the LTC1409ISW#PBF?
The LTC1409ISW#PBF is rated for industrial operation from –40°C to +85°C (I-grade). This is confirmed in the Absolute Maximum Ratings table and applies to all AC/DC specifications including INL, DNL, and S/(N+D) performance. The device uses a thermally compensated internal reference to maintain ±1LSB linearity across this full range, making LTC1409ISW#PBF suitable for outdoor telecom equipment and factory-floor DAQ systems.
Does the LTC1409ISW#PBF require an external clock source?
No, the LTC1409ISW#PBF contains a fully integrated internal clock and does not require an external clock input. Conversion timing is controlled solely by the CONVST signal - a falling edge initiates sampling and conversion. The internal oscillator ensures consistent 800ksps operation without clock jitter sensitivity, simplifying layout and reducing BOM count compared to externally clocked ADCs. This design makes LTC1409ISW#PBF ideal for deterministic real-time systems.
How does the Nap and Sleep shutdown mode work on the LTC1409ISW#PBF?
The LTC1409ISW#PBF implements two distinct low-power states: Nap mode (4mW, 1.2mA total supply current) activates on SHDN low with NAP/SLP high, enabling sub-microsecond wake-up; Sleep mode (10µW, 1µA) activates when both SHDN and NAP/SLP are low. These modes are hardware-controlled and do not require register writes. This dual-tier approach allows LTC1409ISW#PBF to optimize power in burst-mode acquisition systems like portable spectrum analyzers.
Can the LTC1409ISW#PBF interface directly with 3V logic systems?
Yes, the LTC1409ISW#PBF supports direct 3V logic interfacing via its dedicated OVDD pin (Pin 27), which powers the D11–D0 output drivers independently from AVDD. When OVDD is set to 3V, the outputs meet 3V logic thresholds (VOH ≥ 2.4V, VOL ≤ 0.4V) while maintaining full drive strength. This eliminates level shifters in mixed-supply systems and is explicitly validated in the Digital Inputs and Outputs section of the datasheet for LTC1409ISW#PBF.
What is the purpose of the REFCOMP pin on the LTC1409ISW#PBF?
The REFCOMP pin (Pin 4) is the compensation node for the internal reference amplifier that buffers the 2.5V bandgap reference. It must be bypassed to AGND with ≥1µF capacitance (10µF tantalum + 0.1µF ceramic recommended) to ensure stability and low-noise operation. Without proper REFCOMP bypassing, the LTC1409ISW#PBF may exhibit reference oscillation or degraded THD. This requirement is specified in both the Applications Information and Absolute Maximum Ratings sections for LTC1409ISW#PBF.
LTC1409ISW#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 800k
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- ±5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-SOIC
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1409ISW#PBF FAQ
1.How can I place an order for LTC1409ISW#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1409ISW#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1409ISW#PBF reliable?
The price and inventory of LTC1409ISW#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1409ISW#PBF is usually 5 days.
3.What payment methods are accepted for LTC1409ISW#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1409ISW#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1409ISW#PBF?
LTC1409ISW#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1409ISW#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1409ISW#PBF?
For technical support, including LTC1409ISW#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1409ISW#PBF requirements.
6.How does Aetrix verify that LTC1409ISW#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1409ISW#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1409ISW#PBF meets industry standards.
7.What is the process for return or replacement of LTC1409ISW#PBF?
All LTC1409ISW#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1409ISW#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1409ISW#PBF part is unused and in its original packaging.
Return procedure for LTC1409ISW#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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