Analog Devices Inc. LTC1410CG#TRPBF
- Part No.:
- LTC1410CG#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC1410CG#TRPBF.pdf
- Description:
- IC ADC 12BIT SAR 28SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1410CG#TRPBF from Analog Devices (formerly Linear Technology) is a 12-bit, 1.25 Msps successive-approximation ADC with differential input sample-and-hold, internal ±15 ppm/°C reference, and dual shutdown modes (Nap: 7 mW, Sleep: 10 µW). It delivers 71 dB S/(N + D) and 82 dB THD at 625 kHz Nyquist frequency, operating from ±5 V supplies in a 28-pin SO Wide package for high-speed data acquisition systems.
For engineers reviewing the LTC1410CG#TRPBF datasheet, LTC1410CG#TRPBF pinout, LTC1410CG#TRPBF application, or LTC1410CG#TRPBF equivalent, key selection criteria include its 20 MHz full-power bandwidth, ±1 LSB INL/DNL over temperature, no pipeline delay, true differential input architecture with 60 dB CMRR, and µP-compatible parallel interface with BUSY/CONVST/RD control signals.
Technical Context
The LTC1410CG#TRPBF implements a capacitor-based successive approximation register (SAR) architecture with integrated differential sample-and-hold, eliminating external timing components. Its internal clock is factory-trimmed to guarantee ≤750 ns conversion time and ≤800 ns throughput across 0°C to 70°C.
It supports bipolar ±2.5 V analog input range with true differential acquisition (±AIN), enabling common-mode noise rejection without external amplifiers. The device uses separate analog (AGND), digital logic (DGND), and output driver (OGND) grounds, and requires 10 µF tantalum + 0.1 µF ceramic bypassing on VREF, AVDD, DVDD, and VSS per datasheet layout guidelines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonic transfer function for precision measurement. |
| Sampling Rate | 1.25 Msps maximum - enables real-time capture of signals up to 625 kHz Nyquist frequency. |
| S/(N + D) | 71 dB at 600 kHz - ensures ≥11.5 effective bits for high-fidelity spectral analysis. |
| THD | –82 dB at 600 kHz - minimizes harmonic contamination in wideband signal conditioning. |
| INL / DNL | ±1 LSB max over temperature - preserves absolute accuracy in closed-loop control and calibration systems. |
| Full-Power Bandwidth | 20 MHz - supports undersampling of RF IF signals while maintaining SNR integrity. |
| Power Modes | Nap (7 mW) and Sleep (10 µW) - reduces system power by >95% during idle intervals without losing configuration. |
Pinout & Package
Package: 28-lead plastic SO Wide (SW), 0.300-inch body width, RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| +AIN (1) | Differential analog input positive | Accepts ±2.5 V input; sampled simultaneously with –AIN for common-mode rejection. |
| –AIN (2) | Differential analog input negative | Enables ground-sense or true differential measurement; defines common-mode voltage point. |
| VREF (3) | Internal reference output | 2.500 V ±20 mV buffered output; can be overdriven for external reference use (2.25–2.75 V). |
| REFCOMP (4) | Reference amplifier compensation | Requires 10 µF tantalum + 0.1 µF ceramic to AGND for stability and low-noise operation. |
| AGND (5) | Analog ground reference | Single-point star ground for all analog circuitry; must be isolated from digital return paths. |
| D11–D4 (6–13) | MSB-aligned parallel data outputs | Three-state, TTL/CMOS-compatible; driven only when CS = RD = LOW. |
| DGND (14) | Digital logic ground | Tied to AGND; supplies internal control logic and SAR core. |
| D3–D0 (15–18) | LSB-aligned parallel data outputs | Completes 12-bit word; same timing and drive strength as D11–D4. |
| OGND (19) | Output driver ground | Separate return for output buffers; tied to AGND to minimize digital switching noise coupling. |
| NAP/SLP (20) | Shutdown mode select | HIGH = Nap mode (fast wake-up, 200 ns); LOW = Sleep mode (ultra-low power, 10 µW). |
| SHDN (21) | Shutdown enable | Active-low input; asserts selected Nap/Sleep mode when pulled LOW. |
| RD (22) | Data read strobe | Enables output drivers when CS is LOW; data valid on rising edge of BUSY. |
| CONVST (23) | Conversion start | Falling-edge triggered; initiates acquisition and conversion sequence with no pipeline latency. |
| CS (24) | Chip select | Must be LOW to accept CONVST and RD commands; disables outputs when HIGH. |
| BUSY (25) | Conversion status indicator | LOW during conversion; rising edge marks data validity and end of 800 ns throughput cycle. |
| VSS (26) | Negative supply rail | –5 V ±0.25 V; requires local 10 µF + 0.1 µF bypass to AGND. |
| DVDD (27) | Digital positive supply | +5 V ±0.25 V; shorted internally to AVDD (Pin 28) in standard configuration. |
| AVDD (28) | Analog positive supply | +5 V ±0.25 V; bypassed separately with 10 µF + 0.1 µF to AGND for analog integrity. |
Key Features
| Feature | Design Value |
|---|---|
| True differential input architecture | 60 dB common-mode rejection up to 100 kHz enables direct connection to noisy sensor bridges without external instrumentation amps. |
| No pipeline delay | Immediate data availability after BUSY rise eliminates FIFO buffering and simplifies real-time control loop timing. |
| Integrated 2.5 V reference | ±15 ppm/°C tempco and 0.01 LSB/V line regulation ensure stable full-scale span across industrial temperature range. |
| 20 MHz full-power bandwidth | Supports undersampling of IF signals (e.g., 2–5 MHz) in communications receivers while preserving ENOB > 11. |
| Three independent ground pins | AGND/DGND/OGND separation prevents digital switching noise from degrading analog acquisition fidelity. |
Applications
| Telecommunications Baseband Processing | Digital Signal Processing Front-End |
|---|---|
Use Scenario: Digitizing I/Q baseband signals from quadrature demodulators in cellular infrastructure equipment. IC Role / Device Role / Timing Role: High-speed, low-distortion ADC capturing 0–625 kHz complex waveforms with minimal group delay. Use Value: 71 dB S/(N + D) and –82 dB THD preserve EVM performance in LTE/5G NR uplink signal chains. | Use Scenario: Feeding real-time FFT engines in radar pulse-Doppler processors requiring deterministic latency. IC Role / Device Role / Timing Role: Memory-mapped parallel-output ADC synchronized to DSP DMA cycles via BUSY/CONVST handshake. Use Value: No pipeline delay and 800 ns throughput enable sub-microsecond loop closure for adaptive beamforming. |
| Multiplexed Data Acquisition Systems | High-Speed Oscilloscope Channel Digitizer |
Use Scenario: Scanning multiple transducer channels (strain, pressure, temp) in automated test equipment with shared ADC resource. IC Role / Device Role / Timing Role: Precision SAR ADC with Nap mode reducing average power between channel scans. Use Value: ±1 LSB INL ensures traceable calibration across 16+ channels without per-channel correction tables. | Use Scenario: Single-shot transient capture in portable oscilloscopes requiring >1 MS/s sampling with DC-coupled inputs. IC Role / Device Role / Timing Role: Bipolar ±2.5 V input ADC interfaced directly to front-end attenuators and offset DACs. Use Value: True differential inputs reject ground bounce from high-current digital subsystems during fast sweep transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8505IPW | 16-bit, 250 ksps, single-ended input, external reference required | Higher resolution but lower speed; lacks differential input and internal reference | Select for DC-precision applications where throughput < 300 ksps suffices and external reference design is acceptable. |
| AD7865BSZ-1 | 14-bit, 100 ksps, quad-channel, parallel interface, ±5 V supplies | Slower, multi-channel, no Nap/Sleep modes; requires external reference and clock | Choose when simultaneous sampling of four analog signals is needed and power optimization is secondary. |
Compared with ADS8505IPW and AD7865BSZ-1, the LTC1410CG#TRPBF uniquely combines 1.25 Msps speed, integrated reference, differential input, and dual shutdown modes in a single 28-pin SOIC - making it optimal for compact, battery-aware, wideband acquisition where board space and supply simplicity are critical.
Availability
LTC1410CG#TRPBF is available at Aetrix Electronics and suitable for telecommunications baseband processing, digital signal processing front-ends, and multiplexed data acquisition systems requiring stable component supply, long-term lifecycle support, and guaranteed RoHS compliance.
Supply support for LTC1410CG#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC1410CG#TRPBF belongs to ADI's legacy Linear Technology precision data converter product line, engineered for high-speed, low-power, and high-dynamic-range applications where signal integrity and deterministic timing are essential.
FAQ
What is the operating temperature range for the LTC1410CG#TRPBF?
The LTC1410CG#TRPBF is specified for the commercial temperature range of 0°C to 70°C. This is indicated by the "C" suffix in the part number and confirmed in the Absolute Maximum Ratings table, where LTC1410C denotes the 0°C to 70°C grade. The device maintains ±1 LSB INL/DNL and 71 dB S/(N + D) across this full range.
Does the LTC1410CG#TRPBF require an external clock source?
No, the LTC1410CG#TRPBF does not require an external clock. It contains a fully integrated, factory-trimmed internal clock that guarantees ≤750 ns conversion time and 1.25 Msps sampling rate across temperature. The internal clock eliminates synchronization complexity with microprocessor control signals and removes the need for external timing components.
Can the LTC1410CG#TRPBF operate with a single +5 V supply?
No, the LTC1410CG#TRPBF requires dual ±5 V supplies (AVDD = DVDD = +5 V, VSS = –5 V) as specified in the Power Requirements section. Its analog input range is ±2.5 V, and absolute maximum ratings define VSS down to –6 V. Operation with single supply is not supported and would violate the device's bipolar architecture and internal reference design.
How does the NAP/SLP pin affect power consumption of the LTC1410CG#TRPBF?
The NAP/SLP pin selects between two shutdown modes: when HIGH, SHDN activation enters Nap mode (7 mW typical); when LOW, SHDN activation enters Sleep mode (10 µW typical). Both modes retain register state and allow fast wake-up - Nap mode recovers in 200 ns, Sleep mode in <1 µs - enabling dynamic power scaling in burst-mode acquisition systems using the LTC1410CG#TRPBF.
Is the LTC1410CG#TRPBF pin-compatible with other variants in the LTC1410 family?
Yes, the LTC1410CG#TRPBF shares identical pinout and footprint with all 28-pin SO Wide variants (e.g., LTC1410CSW, LTC1410IG, LTC1410ISW). The "G" suffix denotes the SO Wide package, and the "C" denotes commercial temperature grade. Electrical specifications differ by grade (C vs I), but mechanical compatibility and signal routing are preserved across all SW-package LTC1410 devices.
LTC1410CG#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 1.25M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- ±5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 28-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1410CG#TRPBF FAQ
1.How can I place an order for LTC1410CG#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1410CG#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1410CG#TRPBF reliable?
The price and inventory of LTC1410CG#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1410CG#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC1410CG#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1410CG#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1410CG#TRPBF?
LTC1410CG#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1410CG#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1410CG#TRPBF?
For technical support, including LTC1410CG#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1410CG#TRPBF requirements.
6.How does Aetrix verify that LTC1410CG#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC1410CG#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1410CG#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC1410CG#TRPBF?
All LTC1410CG#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1410CG#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1410CG#TRPBF part is unused and in its original packaging.
Return procedure for LTC1410CG#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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