Analog Devices Inc. LTC1411CG#PBF
- Part No.:
- LTC1411CG#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 36-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC1411CG#PBF.pdf
- Description:
- IC ADC 14BIT SAR 36SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1411CG#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 2.5 Msps successive-approximation ADC with integrated sample-and-hold, precision 2.5 V bandgap reference, and programmable ±1.8 V / ±1.27 V / ±0.9 V / ±0.64 V input ranges. It operates from a single 5 V supply, dissipates 195 mW typical, and delivers 80 dB S/(N+D) and ±2 LSB INL over temperature - enabling high-fidelity data acquisition in telecom and DSP systems.
For engineers reviewing the LTC1411CG#PBF datasheet, LTC1411CG#PBF pinout, LTC1411CG#PBF application, or LTC1411CG#PBF equivalent, key selection considerations include its no-pipeline-delay architecture, true differential input rejection, out-of-range (OTR) flag with D13 for over/under detection, Sleep (1 µA) and Nap (2 mA) shutdown modes, and 36-pin SSOP package compatibility with high-density mixed-signal layouts.
Technical Context
The LTC1411CG#PBF employs a capacitor-based successive approximation register (SAR) core with differential sampling, eliminating pipeline latency and enabling deterministic timing critical for real-time control loops. Its internal 2.5 V reference is curvature-corrected and trimmed to ±0.8% initial accuracy with ±15 ppm/°C tempco, and supports external reference via REFIN with 250 µA input current.
Conversion is initiated by a falling edge on CONVST; BUSY goes low for 250–350 ns while the SAR sequences MSB-to-LSB against the internal DAC. Acquisition time is 100 ns with ≤100 Ω source impedance, and aperture jitter is 1 psRMS - ensuring stable ENOB >12.5 bits up to 1 MHz input frequency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with guaranteed no missing codes across 0°C to 70°C operating range |
| Sampling Rate | 2.5 Msps maximum - enables full Nyquist bandwidth of 1.25 MHz for undersampling RF applications |
| S/(N + D) | 80 dB at 100 kHz input - corresponds to ~13.0 effective bits for precision measurement systems |
| INL | ±2 LSB max - ensures monotonicity and <0.00012% full-scale linearity error in sensor interface designs |
| Power Dissipation | 195 mW typical at 2.5 Msps - allows thermal management in compact 36-pin SSOP without forced air |
| Shutdown Current | 1 µA in Sleep mode - supports battery-powered portable instrumentation with rapid wake-up (210 ms) |
| Input Ranges | Four software-selectable spans (±1.8 V, ±1.27 V, ±0.9 V, ±0.64 V) via PGA0/PGA1 pins - eliminates external gain switching |
Pinout & Package
Package: 36-pin plastic SSOP (G package), 0.025" pitch, JEDEC MO-153 compliant, 10.2 mm × 5.3 mm footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN+, AIN− | Differential analog inputs | Accept true differential or single-ended signals; common-mode range = 0 V to VDD; enable >62 dB CMRR for noise rejection |
| REFOUT | 2.5 V internal reference output | Factory-trimmed bandgap source; requires 22 µF tantalum bypass if used to bias AIN−; sets bipolar zero point |
| REFIN | External reference input | Accepts 2.5 V reference (e.g., LT1019A-2.5); 2 kΩ series resistor isolates noise; supports higher precision than internal ref |
| PGA0, PGA1 | Input range select logic inputs | Set one of four gain states (0 dB, –3 dB, –6 dB, –9 dB); control REFCOM2 voltage (4.05 V down to 1.45 V) |
| CONVST | Active-low conversion start | Falling edge triggers SAR cycle; minimum pulse width = 20 ns; no restart during conversion |
| BUSY | Conversion status indicator | Active-low open-drain output; low for 250–350 ns; used to strobe valid data after 7 ns post-BUSY↑ |
| OTR | Out-of-range flag | High when input exceeds ±FSR; combined with D13 (MSB) to distinguish overrange (D13=0, OTR=1) vs underrange (D13=1, OTR=1) |
| D0–D13 | Parallel 14-bit 2's complement data outputs | D13 = MSB; outputs driven to OVDD/OGND rails; compatible with 5 V or 3 V logic families |
| SLP, NAP | Power-down control inputs | SLP↓ → Sleep mode (<1 µA); NAP↓ → Nap mode (2 mA, reference active); both have internal pull-downs |
Key Features
| Feature | Design Value |
|---|---|
| No pipeline delay | Successive-approximation architecture delivers deterministic latency (≤350 ns), enabling closed-loop feedback in motor control |
| Programmable input ranges | Four spans selected via two digital pins - eliminates external PGA and reduces BOM count in multi-range sensor systems |
| Out-of-range detection | Dedicated OTR pin + D13 decoding provides immediate over/under alert without host processor overhead |
| Low-power shutdown modes | Sleep (1 µA) and Nap (2 mA) allow dynamic power scaling in battery-operated spectrum analyzers and portable test gear |
| Internal precision reference | 2.500 V ±0.8% initial accuracy, ±15 ppm/°C tempco - removes need for external reference in cost-sensitive DAQ modules |
| True differential input | Rejects common-mode noise up to 62 dB - critical for industrial signal conditioning in noisy PLC environments |
Applications
| Telecommunications Baseband | Digital Signal Processing |
|---|---|
|
Use Scenario: Digitizing IF signals in cellular basestation receivers before FPGA-based channelization. IC Role / Device Role / Timing Role: High-speed 14-bit sampling front-end with deterministic latency and no pipeline bubbles. Use Value: 80 dB S/(N+D) at 100 kHz preserves EVM in QAM-64 modulation; ±2 LSB INL ensures accurate constellation mapping. |
Use Scenario: Real-time acquisition of vibration spectra from MEMS accelerometers in predictive maintenance edge nodes. IC Role / Device Role / Timing Role: Low-latency analog-to-digital converter interfacing directly to TI C6000 DSP parallel port. Use Value: 2.5 Msps throughput captures 1.25 MHz Nyquist bandwidth; Sleep mode extends battery life between FFT bursts. |
| Multiplexed Data Acquisition | Imaging Systems |
|
Use Scenario: Channelized sampling of 16 thermocouple outputs using external analog multiplexer and cold-junction compensation. IC Role / Device Role / Timing Role: Precision ADC with programmable input ranges matching thermocouple output spans (±15 mV to ±75 mV). Use Value: Four PGA-selectable ranges eliminate per-channel op-amp gain stages; ±2 LSB INL ensures <0.1°C temperature resolution. |
Use Scenario: Line-scan CCD readout in medical X-ray flat-panel detectors requiring low-noise, high-linearity digitization. IC Role / Device Role / Timing Role: Low-jitter (1 psRMS) sampling engine synchronized to pixel clock for artifact-free image capture. Use Value: 90 dB THD at 100 kHz suppresses harmonic distortion in high-contrast edge regions; 100 ns acquisition time supports >10 klines/s scanning. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7865BSZ-1 | 14-bit, 100 kSPS, 5 V single supply; no internal reference; requires external REF; 4-channel simultaneous sampling | Better suited for multi-channel synchronized acquisition (e.g., motor phase current sensing), not high-throughput single-channel use | Select when simultaneous 4-channel sampling is required and speed <100 kSPS suffices; avoid for >1 Msps applications |
| ADS8505IPFBT | 16-bit, 250 kSPS, 5 V supply; includes internal reference and serial interface; no OTR pin; 48-pin TQFP | Higher resolution but lower speed; optimized for precision DC/low-frequency measurements (e.g., weigh scales, power metering) | Select when 16-bit resolution and integrated serial interface outweigh need for 2.5 Msps and OTR functionality |
Compared with AD7865BSZ-1 and ADS8505IPFBT, the LTC1411CG#PBF uniquely balances 14-bit resolution, 2.5 Msps throughput, on-chip reference, OTR flag, and low-power shutdown - making it optimal for space-constrained, high-dynamic-range single-channel acquisition where latency and feature integration matter.
Availability
LTC1411CG#PBF is available at Aetrix Electronics and suitable for telecommunications baseband digitization, digital signal processing front-ends, and multiplexed data acquisition systems requiring stable component supply and long-term industrial availability.
Supply support for LTC1411CG#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC1411CG#PBF belongs to ADI's legacy Linear Technology precision data converter portfolio, designed specifically for high-speed, high-accuracy applications demanding low latency, excellent AC performance, and robust DC specifications in single-supply systems.
FAQ
What is the maximum sampling rate supported by the LTC1411CG#PBF?
The LTC1411CG#PBF supports a guaranteed maximum sampling rate of 2.5 Msps. This is achieved with a typical conversion time of 260 ns and 100 ns acquisition time, resulting in deterministic throughput with no pipeline delay. The device maintains 80 dB S/(N+D) and ±2 LSB INL at this rate, making LTC1411CG#PBF suitable for demanding real-time acquisition tasks such as spectrum analysis and baseband digitization.
Does the LTC1411CG#PBF require an external reference, or does it include an internal one?
The LTC1411CG#PBF includes a factory-trimmed, temperature-compensated 2.5 V bandgap reference accessible at the REFOUT pin. It achieves ±0.8% initial accuracy and ±15 ppm/°C tempco. An external reference can be applied via REFIN for improved stability (e.g., using LT1019A-2.5), but it is not required - the internal reference enables fully self-contained operation in the LTC1411CG#PBF.
How does the out-of-range (OTR) function work on the LTC1411CG#PBF?
The LTC1411CG#PBF provides an OTR pin that asserts high when the analog input exceeds the selected full-scale range. Combined with D13 (MSB), it distinguishes overrange (D13 = 0, OTR = 1) from underrange (D13 = 1, OTR = 1). This dual-signal logic eliminates software polling and enables hardware-triggered clamping or alarm generation - a key differentiator of the LTC1411CG#PBF in fault-tolerant systems.
What are the power-down modes available on the LTC1411CG#PBF, and how do they differ?
The LTC1411CG#PBF offers two hardware-controlled power-down modes: Nap mode (NAP pin low, 2 mA supply current, internal reference remains active) and Sleep mode (SLP pin low, <1 µA supply current, full shutdown). Wake-up from Nap takes 250 ns; from Sleep, it requires 210 ms due to reference stabilization. These modes make LTC1411CG#PBF ideal for burst-mode acquisition in portable instrumentation.
Is the LTC1411CG#PBF compatible with 3 V digital logic interfaces?
Yes - the LTC1411CG#PBF supports dual-voltage operation: AVP and DVP accept 5 V for analog/digital circuitry, while OVDD can be supplied with either 3 V or 5 V to drive the D0–D13, OTR, and BUSY outputs. Output VOH/VOL specs are guaranteed for both 3 V and 5 V OVDD, ensuring direct interfacing with modern 3 V microcontrollers and FPGAs without level-shifting - a verified capability of the LTC1411CG#PBF.
LTC1411CG#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 2.5M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 36-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1411CG#PBF FAQ
1.How can I place an order for LTC1411CG#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1411CG#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1411CG#PBF reliable?
The price and inventory of LTC1411CG#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1411CG#PBF is usually 5 days.
3.What payment methods are accepted for LTC1411CG#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1411CG#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1411CG#PBF?
LTC1411CG#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1411CG#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1411CG#PBF?
For technical support, including LTC1411CG#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1411CG#PBF requirements.
6.How does Aetrix verify that LTC1411CG#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1411CG#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1411CG#PBF meets industry standards.
7.What is the process for return or replacement of LTC1411CG#PBF?
All LTC1411CG#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1411CG#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1411CG#PBF part is unused and in its original packaging.
Return procedure for LTC1411CG#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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