Analog Devices Inc. LTC1536CMS8#PBF

Overview

LTC1536CMS8#PBF from Analog Devices (formerly Linear Technology) is a precision triple supply monitor IC designed for PCI local bus applications. It simultaneously monitors 5V (±5%), 3.3V (±0.3V), and an adjustable input (e.g., 1.000V ±0.75% threshold accuracy), delivers 200ms reset pulse width, features manual pushbutton reset with soft-reset (100µs) and hard-reset (200ms) modes, and meets PCI tFAIL timing specification (≤450ns). It is used in motherboard-level power sequencing and reset generation for multi-rail systems.

For engineers reviewing the LTC1536CMS8#PBF datasheet, LTC1536CMS8#PBF pinout, LTC1536CMS8#PBF application, or LTC1536CMS8#PBF equivalent, key selection considerations include guaranteed reset assertion down to VCC3 ≥ 1V or VCC5 ≥ 1V, open-drain RST/SRST outputs with weak internal 6µA pull-ups to VCC3, glitch immunity via dual-threshold comparators, and MSOP-8 package compatibility with PCI-compliant power-fail response.

Technical Context

The LTC1536CMS8#PBF implements dual-speed comparator architecture per supply rail: a high-accuracy slow comparator (±0.75% threshold tolerance) for stable undervoltage detection, and a fast comparator offset by 250mV for sub-100ns PCI tFAIL/tPF response. Its gate drive circuitry dynamically selects VCC3 or VCC5 as the source for RST output FET control, ensuring valid reset state even when only one supply reaches ≥1V.

Reset logic combines three independent voltage monitoring paths with a 200ms internal timer, pushbutton debouncing (20–35ms), and mode arbitration: PBR assertion <2s triggers SRST (100µs soft reset); PBR ≥2s forces RST low for 200ms after release. Both RST and SRST are open-drain with VCC3-referenced weak pull-ups, enabling OR-tie with other reset sources without level-shifting.

Key Specifications

Pinout & Package

Package: 8-pin MSOP (MS8), 3.0mm × 3.0mm body, 0.65mm pitch, RoHS-compliant lead-free finish (#PBF).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple supply monitoring applications.

Compared with LTC1326CMS8#PBF and TPS3808G33DBVR, the LTC1536CMS8#PBF uniquely integrates PCI-compliant fast-fail detection, dual-mode pushbutton reset, and three independently configurable supply inputs - making it irreplaceable in multi-rail PCI systems requiring field-serviceability and robust brownout recovery.

Availability

LTC1536CMS8#PBF is available at Aetrix Electronics and suitable for PCI expansion board design, motherboard power sequencing, and intelligent instrument supervision requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for LTC1536CMS8#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its precision analog portfolio. Linear pioneered high-accuracy voltage monitoring ICs with industry-leading threshold tolerance and timing performance.

The LTC1536CMS8#PBF belongs to Linear's PCI-compliant power supervisor family, engineered specifically for multi-rail computing platforms where simultaneous 3.3V/5V monitoring, fast fault response, and user-initiated reset are mandatory.

FAQ

What is the minimum operating voltage required for LTC1536CMS8#PBF to assert a valid reset?

The LTC1536CMS8#PBF guarantees correct RST logic state down to VCC3 ≥ 1V or VCC5 ≥ 1V. This means the IC remains functional and asserts reset even during deep brownout conditions where either supply rail collapses to just 1V - a key reliability feature for systems with asymmetric power-down profiles. The LTC1536CMS8#PBF achieves this via dynamic gate drive selection between VCC3 and VCC5 pins.

How does the LTC1536CMS8#PBF differentiate between soft reset and hard reset using the PBR pin?

The LTC1536CMS8#PBF uses internal debounce and timing logic to distinguish PBR press duration: a press shorter than ≈2 seconds (tPB) generates a 100µs soft reset pulse on SRST, while holding PBR low for ≥2 seconds forces the RST output low for 200ms after release. This eliminates external timing components and allows a single pushbutton to serve both recovery and full-reset functions. The LTC1536CMS8#PBF implements this entirely on-die with no firmware or external dependencies.

Does the LTC1536CMS8#PBF meet PCI Local Bus Specification Rev 2.1 for tFAIL timing?

Yes, the LTC1536CMS8#PBF fully complies with PCI Local Bus Specification Rev 2.1 Section 4.3.2 for tFAIL, measuring ≤450ns (typical 150ns) from VCC5 or VCC3 falling 500mV below threshold to RST assertion. This is achieved through dedicated fast comparators with thresholds offset 250mV below the precision trip points. The LTC1536CMS8#PBF also satisfies tPF (VCC5 < VCC3 – 300mV) in ≤90ns, providing margin for system-level timing budgets.

Can the VCCA pin of the LTC1536CMS8#PBF be used to monitor a "power good" signal from a DC/DC converter?

Yes, the VCCA pin is a high-impedance input with a factory-trimmed 1.000V ±0.75% threshold, making it ideal for monitoring DC/DC "power good" outputs or feedback divider nodes. When tied to a 1V logic signal or resistor divider, it extends the LTC1536CMS8#PBF's monitoring capability beyond fixed rails. In typical applications, VCCA is used to hold reset asserted until both 3.3V and 5V are stable *and* the DC/DC converter confirms regulation - a common requirement in server and telecom power systems.

Are the RST and SRST outputs of the LTC1536CMS8#PBF compatible with 5V logic systems?

Yes, both RST (Pin 6) and SRST (Pin 7) are open-drain outputs with weak internal 6µA pull-ups to VCC3, but they tolerate external pull-up voltages up to 7V. This allows direct connection to 5V logic buses when pulled up to VCC5 (or another 5V source) via an external resistor - a standard practice in PCI designs. The LTC1536CMS8#PBF datasheet explicitly permits this configuration and specifies VOL ≤0.4V at ISINK = 2.5mA under such conditions.