Analog Devices Inc. LTC1550CGN#PBF
- Part No.:
- LTC1550CGN#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
LTC1550CGN#PBF.pdf
- Description:
- IC REG CHRG PUMP ADJ 10MA 16SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1550CGN#PBF from Analog Devices (formerly Linear Technology) is an adjustable-output, switched-capacitor negative voltage inverter with integrated linear post-regulator. It generates regulated negative output voltages from a single 2.7V–6.5V positive supply, delivers up to 10mA output current, maintains ±5% output regulation, and achieves <1mVP-P output ripple at 900kHz charge pump frequency - ideal for GaAs FET biasing in portable RF transmitters.
For engineers reviewing the LTC1550CGN#PBF datasheet, LTC1550CGN#PBF pinout, LTC1550CGN#PBF application, or LTC1550CGN#PBF equivalent, this page provides verified functional identity, confirmed SSOP-16 package mapping, validated 16-pin terminal roles, exact output adjustability range (–1.425V to –4.725V), real-world GaAs bias use case, and two manufacturer-confirmed alternative parts with documented technical differences.
Technical Context
The LTC1550CGN#PBF integrates a 900kHz switched-capacitor charge pump followed by a negative linear regulator using an N-channel MOSFET pass device and internal 1.24V reference. Its feedback loop monitors VOUT via SENSE and regulates through ADJ pin using external resistor divider referenced to VOUT-not ground-enabling precise negative output adjustment.
It features TTL-compatible active-low SHDN control (0.2µA shutdown current), dual ground pins (PGND and AGND), and requires only four external capacitors: two 0.1µF charge pump caps (C1+, C1–), one 0.1µF CPOUT cap, and ≥4.7µF output filter (10µF recommended). Output stability and ripple performance are critically dependent on capacitor selection and layout.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Type | Adjustable negative voltage inverter with linear post-regulation |
| Supply Voltage Range | 2.7V to 6.5V - enables operation from single Li-ion or 3.3V/5V rails |
| Max Output Current | 10mA at VCC = 5V - sufficient for GaAs FET gate bias in cellular front-ends |
| Output Regulation | ±5% over load (0–10mA) and input (2.7–6.5V) - guaranteed across commercial temp range |
| Output Ripple | <1mVP-P with 10µF + 0.1µF ceramic output cap - meets low-noise RF bias requirements |
| Charge Pump Freq | 900kHz typical - avoids IF bands (400–600kHz), minimizes capacitor size |
| Shutdown Current | 0.2µA typical - preserves battery life in portable systems during sleep mode |
Pinout & Package
Package: 16-lead plastic SSOP (GN), 0.150" narrow body, JEDEC MS-013AC compliant. Pin pitch: 0.025", body width: 0.150–0.157", height: 0.053–0.069". Thermal resistance θJA = 150°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 NC | No internal connection | Not bonded; must be left floating or tied to GND per layout best practice |
| 2 C1+ | Positive flying capacitor node | Connects to + terminal of 0.1µF charge pump capacitor C1 |
| 3 NC | No internal connection | Not bonded; no routing required |
| 4 VOUT | Negative regulated output | Delivers final adjusted negative voltage; requires ≥4.7µF bypass to AGND/PGND |
| 5 C1– | Negative flying capacitor node | Connects to – terminal of 0.1µF charge pump capacitor C1 |
| 6 PGND | Power ground return | Low-impedance return path for charge pump switching current; tie to AGND at single point |
| 7 AGND | Analog ground reference | Reference for SENSE, REG, ADJ; connect to clean ground plane to minimize regulation error |
| 8 NC | No internal connection | Not bonded; leave unconnected |
| 9 VCC | Positive input supply | Accepts 2.7–6.5V; requires ≥4.7µF bypass capacitor close to pin |
| 10 SHDN | Active-low shutdown control | Pull low to disable charge pump and reduce IQ to 0.2µA; TTL-compatible |
| 11 REG | Open-drain regulation status flag | Pulls low when VOUT within ±5%; requires external pull-up to monitor regulation health |
| 12 SENSE | Output voltage sense input | Direct connection to VOUT improves regulation accuracy; route short and direct |
| 13 ADJ | Feedback input for output adjustment | Accepts voltage divider tap from VOUT to AGND; sets output via 1.24V internal reference |
| 14 CPOUT | Negative charge pump output | Intermediate negative rail feeding linear regulator; bypass to PGND with 0.1µF cap |
| 15 NC | No internal connection | Not bonded; no routing required |
| 16 NC | No internal connection | Not bonded; no routing required |
Key Features
| Feature | Design Value |
|---|---|
| Adjustable negative output | Configurable from –1.425V to –4.725V using external resistor divider on ADJ pin |
| Ultra-low output noise | <1mVP-P ripple with proper capacitor selection - critical for RF transmitter linearity |
| Single-supply operation | Operates from 2.7V–6.5V - supports modern low-voltage battery and logic rails |
| Integrated linear post-regulator | Eliminates need for external LDO; provides fast transient response and tight regulation |
| Low-power shutdown | 0.2µA quiescent current in shutdown - extends battery runtime in portable devices |
Applications
| GaAs FET Transmitter Bias | Portable RF Power Amplifier Supply |
|---|---|
Use Scenario: Generating stable negative gate bias for GaAs pHEMT power amplifiers in 3G/4G cellular handsets. IC Role / Device Role / Timing Role: Adjustable negative voltage inverter providing precise, low-noise VGS control to set amplifier operating point. Use Value: Enables accurate bias setting across temperature and process variation while maintaining <1mVP-P ripple to prevent AM-to-PM distortion. |
Use Scenario: Supplying regulated negative voltage to RF front-end ICs requiring dual-rail operation in compact IoT modules. IC Role / Device Role / Timing Role: Compact, capacitor-based negative rail generator replacing discrete inductor-based solutions. Use Value: Reduces BOM count and PCB area versus inductive DC/DC; eliminates EMI concerns from magnetic components. |
| Low-Noise Analog Signal Chain Bias | Industrial Sensor Interface Supply |
Use Scenario: Providing clean negative reference for precision op-amp circuits in battery-powered data loggers. IC Role / Device Role / Timing Role: Low-ripple negative supply source for rail-to-rail input/output amplifiers and ADC drivers. Use Value: Maintains SNR integrity in µV-level signal paths by minimizing switching artifacts coupled into analog sections. |
Use Scenario: Generating isolated negative bias for MEMS sensor excitation or piezoelectric transducer drive in field instruments. IC Role / Device Role / Timing Role: Regulated negative voltage source tolerant of wide input voltage swings and temperature extremes. Use Value: Ensures consistent sensor bias across –40°C to +85°C industrial operating range with ±5% regulation guarantee. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar negative voltage inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC1551CS8-4.1 | Fixed –4.1V output, SO-8 package, active-high SHDN, 4.5–6.5V VCC range | Not adjustable; limited to fixed-bias applications; smaller footprint but no output tuning | Select when fixed –4.1V output suffices and board space is constrained; not suitable for variable bias needs. |
| LTC1261CS8-5 | Fixed –5V output, SO-8, no internal linear regulator, higher ripple (~5mVP-P) | Lacks post-regulation - requires external filtering for low-noise apps; lower cost but higher design overhead | Choose for cost-sensitive, non-critical bias where ripple tolerance >3mVP-P and regulation accuracy <±10% is acceptable. |
Compared with LTC1550CGN#PBF, LTC1551CS8-4.1 offers pin-compatible simplicity for fixed-voltage use but forfeits adjustability, while LTC1261CS8-5 reduces cost and complexity at the expense of regulation precision and noise performance - making LTC1550CGN#PBF the sole choice for applications demanding tunable, ultra-low-noise negative bias.
Availability
LTC1550CGN#PBF is available at Aetrix Electronics and suitable for GaAs FET biasing, portable RF power amplifier supply, and low-noise analog signal chain biasing requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC1550CGN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for legacy Linear parts including the LTC series.
The LTC1550 family was designed specifically for high-efficiency, low-noise negative voltage generation in space-constrained RF and portable electronics - emphasizing capacitor-based simplicity, GaAs FET compatibility, and robust regulation under dynamic load conditions.
FAQ
What output voltage range can the LTC1550CGN#PBF generate?
The LTC1550CGN#PBF supports adjustable negative output voltages from –1.425V to –4.725V, determined by an external resistor divider connected between AGND and VOUT with the tap at ADJ. The internal 1.24V reference and feedback architecture enable precise setting - for example, a –3.0V output requires ~13kΩ from AGND to ADJ and ~9.1kΩ from ADJ to VOUT. All values are validated per the Electrical Characteristics table across 2.7–6.5V VCC and 0–10mA load.
How does the LTC1550CGN#PBF achieve sub-1mVP-P output ripple?
The LTC1550CGN#PBF achieves <1mVP-P output ripple through a two-stage architecture: a 900kHz switched-capacitor charge pump followed by a linear post-regulator with fast transient response. Critical to meeting this spec is using a ≥10µF output capacitor (e.g., tantalum) paralleled with a 0.1µF ceramic capacitor at VOUT, plus proper layout of SENSE routed directly to the load. This combination suppresses both fundamental switching noise and high-frequency spikes, as confirmed in Figure 5 of the datasheet.
What is the function of the REG pin on the LTC1550CGN#PBF?
The REG pin on the LTC1550CGN#PBF is an open-drain output that pulls low when the regulated VOUT is within ±5% of its target value. It sinks up to 7mA with a 5V supply and requires an external pull-up resistor to monitor regulation status. This pin enables system-level fault detection - for instance, asserting a microcontroller interrupt if REG remains high, indicating loss of regulation due to overload, input undervoltage, or capacitor failure - a feature unique to the LTC1550CGN#PBF among its family variants.
Can the LTC1550CGN#PBF operate from a 3.3V supply?
Yes, the LTC1550CGN#PBF is explicitly rated for VCC = 2.7V to 6.5V, making it fully compatible with 3.3V systems. At 3.3V input, it can deliver regulated outputs down to –1.425V (per Electrical Characteristics table, 2.7V ≤ VCC ≤ 6.5V, 0 ≤ IOUT ≤ 5mA). Output current capability scales with input voltage - e.g., maximum 10mA is guaranteed only above 4.75V VCC for –4.1V output - so design margins must be verified per the Typical Performance Characteristics graphs.
Why does the LTC1550CGN#PBF require separate PGND and AGND pins?
The LTC1550CGN#PBF separates PGND (power ground for charge pump switching currents) and AGND (analog ground for SENSE, REG, and ADJ reference) to prevent noise coupling from high di/dt switching events into the sensitive regulation feedback path. Layout best practice requires connecting PGND and AGND at a single point near the device, with AGND tied to a clean ground plane. This separation is essential to maintain ±5% regulation accuracy and <1mVP-P ripple - a requirement confirmed in the Applications Information section and Pin Functions description.
LTC1550CGN#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Negative
- Topology:
- Charge Pump
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 6.5V
- Voltage - Output (Min/Fixed):
- -1.24V
- Voltage - Output (Max):
- -6.1V
- Current - Output:
- 10mA
- Frequency - Switching:
- 900kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
LTC1550CGN#PBF FAQ
1.How can I place an order for LTC1550CGN#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1550CGN#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1550CGN#PBF reliable?
The price and inventory of LTC1550CGN#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1550CGN#PBF is usually 5 days.
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Once your LTC1550CGN#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1550CGN#PBF?
For technical support, including LTC1550CGN#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1550CGN#PBF requirements.
6.How does Aetrix verify that LTC1550CGN#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1550CGN#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1550CGN#PBF meets industry standards.
7.What is the process for return or replacement of LTC1550CGN#PBF?
All LTC1550CGN#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1550CGN#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1550CGN#PBF part is unused and in its original packaging.
Return procedure for LTC1550CGN#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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