Analog Devices Inc. LTC1550IGN#PBF
- Part No.:
- LTC1550IGN#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
LTC1550IGN#PBF.pdf
- Description:
- IC REG CHRG PUMP ADJ 10MA 16SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1550IGN#PBF from Analog Devices (formerly Linear Technology) is an adjustable-output, low-noise switched-capacitor voltage inverter with integrated linear post-regulator. It generates regulated negative voltages from a single 2.7V–6.5V positive supply, delivers up to 10mA output current, maintains ±5% output regulation, and achieves <1mVP-P output ripple at 900kHz charge pump frequency. It serves as a precision GaAs FET bias generator in portable RF transmitters.
For engineers reviewing the LTC1550IGN#PBF datasheet, LTC1550IGN#PBF pinout, LTC1550IGN#PBF application, or LTC1550IGN#PBF equivalent, this page provides verified functional identity, SSOP-16 package mapping, confirmed adjustable-output behavior, shutdown current <1µA, and validated alternative options for negative bias generation in battery-powered RF systems.
Technical Context
The LTC1550IGN#PBF integrates a 900kHz switched-capacitor charge pump followed by a negative linear regulator using an N-channel MOSFET pass device and internal 1.24V reference. Its ADJ pin accepts an external resistor divider referenced to VOUT to set output voltage across multiple ranges (e.g., –1.5V to –4.7V), while SENSE enables remote sensing for improved load regulation.
It operates with only four external capacitors (two 0.1µF charge pump caps, one ≥4.7µF output cap, one ≥4.7µF input bypass cap), supports active-low TTL-compatible shutdown (SHDN), and features REG open-drain flag indicating ±5% regulation status. The 16-pin SSOP package separates PGND and AGND for noise-sensitive analog regulation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Type | Adjustable negative voltage (set via ADJ pin resistor divider) |
| Supply Voltage Range | 2.7V to 6.5V - enables operation from single Li-ion or dual-cell alkaline supplies |
| Max Output Current | 10mA at VCC = 5V - sufficient for GaAs FET gate bias in cellular PA stages |
| Output Regulation | ±5% over load (0–10mA) and input (2.7–6.5V) - ensures stable bias under varying battery discharge |
| Output Ripple | <1mVP-P - achieved with 10µF + 0.1µF ceramic output capacitor, critical for RF signal integrity |
| Shutdown Current | <1µA - extends battery life in standby mode of portable transceivers |
| Charge Pump Frequency | 900kHz - avoids IF bands (400–600kHz), reduces capacitor size, minimizes EMI coupling |
Pinout & Package
Package: 16-lead plastic SSOP (GN), 0.150" narrow body, exposed pad not present, JEDEC MS-013AC compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 15, 16 | NC | No internal connection - must be left floating or tied to GND per layout best practice |
| 2 | C1+ | Positive terminal of flying capacitor - connects to C1+ side of 0.1µF charge pump capacitor |
| 4 | VOUT | Regulated negative output - requires ≥4.7µF capacitor to AGND/PGND for loop stability |
| 5 | C1− | Negative terminal of flying capacitor - connects to C1− side of same 0.1µF charge pump capacitor |
| 6 | PGND | Power ground - low-impedance return path for charge pump switching current |
| 7 | AGND | Analog ground - isolated reference for regulator feedback; must tie to PGND at single point |
| 8 | VCC | Positive supply input - bypassed with ≥4.7µF capacitor close to pin to prevent supply droop |
| 9 | SHDN | Active-low shutdown control - pulls low to disable charge pump and reduce IQ to <1µA |
| 10 | REG | Open-drain regulation flag - sinks 7mA when output is within ±5%; requires external pull-up |
| 11 | SENSE | Feedback sense node - connected directly to VOUT near load to compensate for trace IR drop |
| 12 | ADJ | Adjustable feedback input - sets output voltage via resistor divider from AGND to VOUT |
| 13 | CPOUT | Negative charge pump output - drives linear regulator input; requires 0.1µF storage capacitor to PGND |
| 14 | NC | No internal connection - must be left floating |
Key Features
| Feature | Design Value |
|---|---|
| Adjustable output voltage | Configurable from –1.5V to –4.7V using external resistors on ADJ pin - eliminates need for multiple fixed-voltage SKUs |
| Integrated linear post-regulator | Reduces charge pump ripple to <1mVP-P - enables direct use in sensitive RF bias applications without additional filtering |
| Dual ground separation (PGND/AGND) | Minimizes switching noise coupling into regulation loop - improves PSRR and load transient response |
| 900kHz fixed-frequency oscillator | Enables consistent EMI profile and predictable capacitor sizing - avoids interference with common IF bands |
| TTL-compatible active-low SHDN | Reduces quiescent current to <1µA - supports ultra-low-power sleep modes in battery-operated handhelds |
Applications
| Portable RF Transmitter Bias | GaAs FET Gate Control |
|---|---|
|
Use Scenario: Providing stable negative gate bias to GaAs power amplifier FETs in GSM/CDMA handsets during transmit bursts. IC Role / Device Role / Timing Role: Adjustable negative voltage generator with fast transient response and ultra-low ripple. Use Value: Maintains consistent FET transconductance across battery discharge (2.7–6.5V), preventing gain drift and spectral regrowth. |
Use Scenario: Generating precise –3.0V gate voltage for enhancement-mode GaAs pHEMT drivers in 2.4GHz Wi-Fi modules. IC Role / Device Role / Timing Role: Regulated inverting charge pump with remote SENSE feedback for load-point accuracy. Use Value: Enables accurate threshold tracking via ADJ-resistor tuning, reducing calibration overhead in production test. |
| Battery-Powered Instrumentation | Low-Noise Signal Chain Bias |
|
Use Scenario: Supplying clean –4.1V rail for op-amp dual-supply circuits in handheld multimeters and sensor loggers. IC Role / Device Role / Timing Role: Low-quiescent, low-ripple negative supply with shutdown control for power cycling. Use Value: Extends AA/AAA battery life beyond 100 hours while maintaining ADC reference stability and offset performance. |
Use Scenario: Biasing high-speed comparators and ADC drivers requiring symmetric ±5V rails from a single 5V source. IC Role / Device Role / Timing Role: Post-regulated inverter delivering sub-mVP-P noise floor compatible with 16-bit precision. Use Value: Eliminates need for discrete LDO + inverter combo, reducing BOM count and PCB area by 40%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar negative voltage generation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC1550CGN#PBF | Same die, identical electrical specs, but marked CGN instead of IGN - both are 16-pin SSOP, adjustable, -40°C to 85°C industrial grade | No functional difference - IGN and CGN denote same temperature grade and performance; IGN is standard ordering suffix | Select LTC1550IGN#PBF for guaranteed availability and full traceability; CGN may have older date codes or alternate packaging |
| MAX680ESA+ | Fixed –5V output, no ADJ pin, no SENSE, higher 1200kHz fOSC, 20mA IOUT, SO-8 package only | Suitable for non-adjustable, higher-current applications where ±5% regulation and <1mVP-P ripple are less critical | Choose MAX680ESA+ only if fixed –5V suffices and board space constraints favor SO-8; not drop-in due to pinout and adjustability mismatch |
Compared with LTC1550IGN#PBF, LTC1550CGN#PBF offers identical functionality and spec compliance, while MAX680ESA+ trades adjustability and ultra-low ripple for higher output current and smaller footprint - making it suitable only for fixed-rail, less noise-sensitive designs.
Availability
LTC1550IGN#PBF is available at Aetrix Electronics and suitable for portable RF transmitters, GaAs FET bias networks, and battery-powered instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed industrial-grade temperature performance.
Supply support for LTC1550IGN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, datasheet archives, and application engineering for legacy Linear parts including the LTC family.
The LTC1550IGN#PBF belongs to Linear's precision switched-capacitor voltage inverter product line, designed specifically for low-noise, battery-efficient negative bias generation in portable wireless infrastructure and RF front-end modules.
FAQ
What output voltage range can the LTC1550IGN#PBF generate?
The LTC1550IGN#PBF supports adjustable negative output voltages from approximately –1.5V to –4.7V, set by an external resistor divider connected between AGND and VOUT with the tap at ADJ. Specific values depend on VCC and load conditions - for example, –4.1V is achievable with VCC ≥ 4.5V and IOUT ≤ 10mA. The LTC1550IGN#PBF datasheet provides regulation curves across all combinations.
How does the SENSE pin improve regulation accuracy in the LTC1550IGN#PBF?
The SENSE pin on the LTC1550IGN#PBF enables remote sensing of the actual VOUT voltage at the load, compensating for IR drop across PCB traces. By connecting SENSE directly to the load-side of the output capacitor, the LTC1550IGN#PBF adjusts its internal regulation loop to maintain ±5% accuracy at the point of use - critical for GaAs FET gate bias stability under dynamic current loads.
Can the LTC1550IGN#PBF operate from a 3.3V supply?
Yes - the LTC1550IGN#PBF is specified for VCC from 2.7V to 6.5V, so it functions reliably from a 3.3V supply. However, maximum output current decreases at lower VCC; for instance, at VCC = 3.3V, the LTC1550IGN#PBF delivers ~5mA while maintaining ±5% regulation. Always consult the "Maximum Output Current vs Supply Voltage" graph in the LTC1550IGN#PBF datasheet for design margining.
What is the purpose of separate PGND and AGND pins on the LTC1550IGN#PBF?
The LTC1550IGN#PBF uses separate PGND (power ground) and AGND (analog ground) pins to isolate high-current charge pump switching noise from the sensitive linear regulator feedback path. PGND carries pulsed currents from C1 and CPOUT, while AGND serves as the quiet reference for SENSE, ADJ, and REG. They must be joined at a single low-impedance point - typically under the IC or at the input capacitor - to prevent ground loops and ensure stable regulation.
Does the LTC1550IGN#PBF require external components beyond capacitors?
Yes - in addition to the four required capacitors (CIN ≥4.7µF, C1 = CCP = 0.1µF, COUT ≥4.7µF), the LTC1550IGN#PBF needs two external resistors for adjustable output configuration: one from AGND to ADJ and another from ADJ to VOUT. These form a feedback divider that sets the output voltage based on the internal 1.24V reference. No inductors or diodes are required - the LTC1550IGN#PBF is a fully integrated charge pump + LDO solution.
LTC1550IGN#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Negative
- Topology:
- Charge Pump
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 6.5V
- Voltage - Output (Min/Fixed):
- -1.24V
- Voltage - Output (Max):
- -6.1V
- Current - Output:
- 10mA
- Frequency - Switching:
- 900kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
LTC1550IGN#PBF FAQ
1.How can I place an order for LTC1550IGN#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1550IGN#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1550IGN#PBF reliable?
The price and inventory of LTC1550IGN#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1550IGN#PBF is usually 5 days.
3.What payment methods are accepted for LTC1550IGN#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1550IGN#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1550IGN#PBF?
LTC1550IGN#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1550IGN#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1550IGN#PBF?
For technical support, including LTC1550IGN#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1550IGN#PBF requirements.
6.How does Aetrix verify that LTC1550IGN#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1550IGN#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1550IGN#PBF meets industry standards.
7.What is the process for return or replacement of LTC1550IGN#PBF?
All LTC1550IGN#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1550IGN#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1550IGN#PBF part is unused and in its original packaging.
Return procedure for LTC1550IGN#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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