Analog Devices Inc. LTC1603CG#PBF
- Part No.:
- LTC1603CG#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 36-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC1603CG#PBF.pdf
- Description:
- IC ADC 16BIT SAR 36SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1603CG#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 250ksps successive-approximation analog-to-digital converter with true differential inputs, ±2.5V bipolar input range, 90dB S/(N+D), and –100dB THD at 5kHz - deployed in high-speed data acquisition systems requiring precision timing and low-noise signal capture.
For engineers reviewing the LTC1603CG#PBF datasheet, LTC1603CG#PBF pinout, LTC1603CG#PBF application, or LTC1603CG#PBF equivalent, key selection criteria include its no-pipeline-delay parallel interface, dual shutdown modes (7mW Nap / 10µW Sleep), internal 2.5V reference with 15ppm/°C tempco, and 36-pin SSOP package compatibility with LTC1604/LTC1608.
Technical Context
The LTC1603CG#PBF implements a capacitor-based SAR architecture with an integrated differential sample-and-hold front-end, factory-trimmed internal clock (3.3µs typical conversion time), and two-stage power management logic enabling Nap and Sleep modes via SHDN/CS pin combination. Its analog core operates from ±5V supplies, while digital outputs are independently powered via OVDD for 3V/5V system interfacing.
It features a 15MHz small-signal input bandwidth, 68dB common-mode rejection up to 100kHz, and full-scale linearity maintained across 0°C to 70°C - validated by guaranteed no missing codes and ±3 LSB integral nonlinearity over temperature. The 16-bit parallel output delivers two's complement data synchronized to BUSY rising edge with zero pipeline latency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit with guaranteed no missing codes over full operating temperature range |
| Sampling Rate | 250ksps maximum throughput - enables real-time capture of signals up to 125kHz Nyquist bandwidth |
| S/(N+D) Ratio | 90dB at 5kHz input - supports high-fidelity digitization in spectrum analysis and imaging applications |
| THD | –100dB at 5kHz (up to 5th harmonic) - ensures minimal harmonic distortion in precision measurement systems |
| Power Dissipation | 220mW typical at 250ksps; reduces to 7mW in Nap mode and 10µW in Sleep mode |
| Input Range | ±2.5V differential - allows direct connection to op-amp buffers without level-shifting circuitry |
| Reference | Internal 2.5V bandgap reference with ±15ppm/°C tempco - eliminates need for external reference in most applications |
Pinout & Package
Package: 36-lead plastic SSOP (G package), 0.209" body width, 0.025" lead pitch, RoHS-compliant, Pb-free (LTC1603CG#PBF designation confirms #PBF suffix).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN+ (1), AIN– (2) | Differential analog input pair | Accepts ±2.5V differential signal; enables common-mode noise rejection and rail-to-rail input operation |
| VREF (3) | 2.5V reference output | Provides buffered internal reference; can be overdriven by external reference (e.g., LT1019A-2.5) for span adjustment |
| REFCOMP (4) | Reference amplifier compensation node | Requires 47µF tantalum + 0.1µF ceramic bypass to AGND for stable 4.375V bias generation |
| AGND (5–8) | Analog ground terminals | Four dedicated analog ground pins minimize ground bounce and improve PSRR in mixed-signal layouts |
| DVDD (9), DGND (10) | Digital logic supply and ground | Isolates digital control logic from analog section; decoupling required per datasheet layout guidelines |
| D15–D0 (11–26) | 16-bit three-state parallel data outputs | Two's complement format; output voltage swing controlled by OVDD pin for 3V/5V bus compatibility |
| BUSY (27) | Conversion status indicator | Active-low open-drain output; rising edge marks valid data ready - used for synchronous latching without additional timing logic |
| OGND (28), OVDD (29) | Output driver supply and ground | Separate power domain for D[15:0] and BUSY outputs - enables interoperability with 3V microcontrollers while AVDD/DVDD run at ±5V |
| RD (30), CONVST (31), CS (32) | Control interface inputs | Standard memory-mapped interface: CS enables device, CONVST starts conversion on falling edge, RD gates output drivers |
| SHDN (33) | Power shutdown control | Combined with CS state selects Nap (CS low) or Sleep (CS high) mode - wake-up times are 200ns and >160ms respectively |
| VSS (34) | Negative analog supply | –5V supply rail; requires local 10µF tantalum + 0.1µF ceramic decoupling to AGND |
| AVDD (35, 36) | Positive analog supply (dual pins) | 5V analog supply; pins tied externally via 10Ω resistor to reduce supply coupling between analog sections |
Key Features
| Feature | Design Value |
|---|---|
| No pipeline delay | Immediate availability of conversion result on BUSY rising edge - eliminates FIFO buffering and simplifies real-time control loop design |
| Dual shutdown modes | Nap mode (7mW) retains reference and digital logic for fast wake-up; Sleep mode (10µW) shuts down all bias currents except leakage |
| True differential input architecture | 68dB CMRR up to 100kHz enables rejection of ground loops and EMI in noisy industrial environments |
| Internal precision reference | 2.5V ±0.125% full-scale error with 15ppm/°C tempco - eliminates external reference component count and layout area |
| 3V/5V digital interface compatibility | OVDD-controlled outputs and 3V-tolerant inputs allow seamless integration with modern low-voltage microcontrollers and FPGAs |
| Pin compatibility with LTC1604/LTC1608 | Same 36-pin SSOP footprint and pinout - enables drop-in migration between 16-bit/14-bit/12-bit variants without PCB redesign |
Applications
| Telecommunications Baseband Processing | Digital Signal Processing Front-End |
|---|---|
Use Scenario: Digitizing IF signals in cellular base station receivers prior to FPGA-based demodulation and channel filtering. IC Role / Device Role / Timing Role: High-linearity ADC capturing 125kHz bandwidth signals with minimal harmonic distortion and jitter-induced SNR degradation. Use Value: 90dB S/(N+D) and –100dB THD preserve modulation accuracy for QAM-64/256 constellations; no pipeline delay enables deterministic sampling alignment with FPGA clock domains. |
Use Scenario: Sampling sensor outputs in real-time DSP systems performing FFT-based spectral analysis or adaptive filtering. IC Role / Device Role / Timing Role: Precision data acquisition engine feeding TI C6000 or Analog Devices SHARC processors via parallel bus. Use Value: 16-bit resolution and ±3 LSB INL ensure accurate amplitude representation across full dynamic range; BUSY-synchronized read avoids metastability in high-throughput processing pipelines. |
| Multiplexed Data Acquisition Systems | Imaging System Digitization |
Use Scenario: Channelized acquisition in automated test equipment where multiple sensors share a single ADC via analog multiplexer. IC Role / Device Role / Timing Role: High-speed sampling node with fast acquisition time (480ns) and low input capacitance (5pF during conversion) minimizing crosstalk and settling errors. Use Value: Differential input rejects common-mode noise induced by multiplexer switching transients; Nap mode reduces average power during inter-channel idle periods. |
Use Scenario: Converting analog video or X-ray detector outputs in medical or industrial imaging systems requiring wide dynamic range and low noise floor. IC Role / Device Role / Timing Role: High-fidelity digitizer preserving contrast and detail in low-light or high-resolution image capture. Use Value: 5MHz full-power bandwidth supports pixel clock rates up to 250Msps equivalent; 90dB SNR enables >15-bit effective resolution for grayscale fidelity in diagnostic imaging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed, high-resolution ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8556IPM (Texas Instruments) | 6-channel simultaneous-sampling 16-bit SAR ADC; 600ksps per channel; requires external reference and separate power domains for analog/digital sections | Designed for multi-channel synchronized acquisition (e.g., motor phase current sensing); lacks integrated reference and differential input flexibility | Select when simultaneous sampling across ≥2 channels is required; avoid if single-channel cost, board space, or simplicity are priorities |
| AD7606BSTZ (Analog Devices) | 8-channel 16-bit SAR ADC with on-chip reference, 200ksps per channel, ±10V/±5V input range; uses serial interface (SPI) instead of parallel | Optimized for industrial PLC I/O modules; lower sampling rate but higher channel density and built-in oversampling filter | Select for multi-input systems needing SPI interface and integrated protection; avoid if parallel bus timing determinism or 250ksps single-channel throughput is mandatory |
Compared with ADS8556IPM and AD7606BSTZ, the LTC1603CG#PBF delivers superior single-channel speed (250ksps vs. 200–600ksps shared across channels), integrated reference, and true differential input architecture - making it optimal for applications prioritizing timing precision, noise immunity, and minimal BOM count in compact designs.
Availability
LTC1603CG#PBF is available at Aetrix Electronics and suitable for telecommunications infrastructure, digital signal processing front-ends, and high-speed data acquisition systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC1603CG#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC1603CG#PBF belongs to Linear Technology's precision high-speed data converter product line, designed specifically for applications demanding low-noise, low-distortion digitization with minimal system-level complexity and power consumption.
FAQ
What is the operating temperature range for the LTC1603CG#PBF?
The LTC1603CG#PBF is specified for commercial-grade operation from 0°C to 70°C. This is indicated by the "C" suffix in the part number. The "G" denotes the grade meets all guaranteed specifications across this full temperature range - including integral linearity error (±3 LSB), offset tempco (0.5 ppm/°C), and S/(N+D) performance (90dB minimum). Industrial-grade variant LTC1603IG extends to –40°C to 85°C.
Does the LTC1603CG#PBF require an external clock source?
No, the LTC1603CG#PBF does not require an external clock source. It contains a factory-trimmed internal oscillator that guarantees a maximum conversion time of 3.8µs and a minimum sampling rate of 250ksps across temperature. The internal clock eliminates timing jitter from external sources and simplifies system design - no crystal, PLL, or clock distribution network is needed for basic operation.
How does the LTC1603CG#PBF handle differential versus single-ended inputs?
The LTC1603CG#PBF natively supports both configurations. In differential mode (AIN+ and AIN– driven), it achieves 68dB CMRR and full 16-bit linearity. In single-ended mode (AIN– grounded), it maintains ±2.5V input range on AIN+, with linearity specs unchanged. The sample-and-hold acquires both inputs simultaneously, so common-mode rejection is preserved even with mismatched source impedances - a key advantage over pseudo-differential architectures.
What are the wake-up times from Nap and Sleep modes for the LTC1603CG#PBF?
Wake-up from Nap mode (SHDN low, CS low) takes 200ns - sufficient for burst-mode acquisition in real-time control systems. Wake-up from Sleep mode (SHDN low, CS high) depends on REFCOMP capacitor value; with the recommended 47µF, it is 160ms due to reference circuit settling. The LTC1603CG#PBF must complete this settling before valid conversions resume - critical for applications requiring rapid power cycling.
Can the LTC1603CG#PBF interface directly with a 3.3V microcontroller?
Yes, the LTC1603CG#PBF supports direct 3.3V interface via its dedicated OVDD pin. When OVDD = 3.3V, the D[15:0] outputs and BUSY signal swing between 0V and 3.3V, while digital inputs (CS, CONVST, RD, SHDN) accept 3V logic levels per VIH/VIL specs. This eliminates level shifters - the analog section continues operating from ±5V supplies, preserving dynamic performance independent of digital interface voltage.
LTC1603CG#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 250k
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- ±5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 36-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1603CG#PBF FAQ
1.How can I place an order for LTC1603CG#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1603CG#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1603CG#PBF reliable?
The price and inventory of LTC1603CG#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1603CG#PBF is usually 5 days.
3.What payment methods are accepted for LTC1603CG#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1603CG#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1603CG#PBF?
LTC1603CG#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1603CG#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1603CG#PBF?
For technical support, including LTC1603CG#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1603CG#PBF requirements.
6.How does Aetrix verify that LTC1603CG#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1603CG#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1603CG#PBF meets industry standards.
7.What is the process for return or replacement of LTC1603CG#PBF?
All LTC1603CG#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1603CG#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1603CG#PBF part is unused and in its original packaging.
Return procedure for LTC1603CG#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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