Analog Devices Inc. LTC1603CG#TRPBF
- Part No.:
- LTC1603CG#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 36-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC1603CG#TRPBF.pdf
- Description:
- IC ADC 16BIT SAR 36SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1603CG#TRPBF from Analog Devices (formerly Linear Technology) is a 16-bit, 250ksps successive-approximation analog-to-digital converter with differential input, internal 2.5V reference, ±2.5V bipolar input range, and 90dB S/(N+D) at 250ksps. It operates from ±5V supplies, draws 220mW typical power, and targets high-speed data acquisition in spectrum analysis and imaging systems.
For engineers reviewing the LTC1603CG#TRPBF datasheet, LTC1603CG#TRPBF pinout, LTC1603CG#TRPBF application, or LTC1603CG#TRPBF equivalent, key selection factors include its no-pipeline-delay parallel output, 68dB common-mode rejection, Nap/Sleep shutdown modes (7mW / 10µW), 480ns acquisition time, and compatibility with µP/DSP interfaces via CS/CONVST/RD control.
Technical Context
The LTC1603CG#TRPBF implements a capacitor-based successive-approximation register (SAR) architecture with integrated differential sample-and-hold, eliminating pipeline latency and guaranteeing no missing codes over temperature. Its internal 15ppm/°C bandgap reference feeds a 1.75× gain reference amplifier, delivering stable 2.500V at VREF and 4.375V at REFCOMP.
Digital interface timing is governed by an internal factory-trimmed clock (3.3µs typical conversion time), supporting three operational modes: always-enabled outputs (Mode 1), RD-gated reads (Mode 2), and CONVST-RD combined slow-memory/ROM modes. Input acquisition bandwidth is 15MHz, with full-power bandwidth specified at 5MHz and linear bandwidth (S/(N+D) ≥84dB) at 350kHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit with guaranteed no missing codes over 0°C to 70°C |
| Sampling Rate | 250ksps maximum throughput, enabled by 4µs acquisition + conversion time |
| S/(N+D) Ratio | 90dB at 5kHz input - defines usable dynamic range for low-distortion signal capture |
| THD | –100dB at 5kHz - enables clean spectral analysis up to Nyquist (125kHz) |
| Input Range | ±2.5V differential - supports direct connection to op-amp buffers without level-shifting |
| Power Modes | Nap mode (7mW) and Sleep mode (10µW) - reduce system standby power without external sequencing |
| Common-Mode Rejection | 68dB - suppresses ground-loop noise and enables true differential measurement from source |
| Reference | Internal 2.500V ±15ppm/°C - eliminates need for external precision reference in cost-sensitive designs |
Pinout & Package
The LTC1603CG#TRPBF is housed in a 36-pin plastic SSOP (Shrink Small Outline Package) with exposed pad thermal enhancement, compatible with standard surface-mount reflow processes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN+ (1), AIN– (2) | Differential analog input pair | Accepts ±2.5V differential signals; 15MHz acquisition bandwidth enables wideband signal capture |
| VREF (3) | 2.5V reference output | Provides buffered internal reference; bypassed with 2.2µF tantalum + 0.1µF ceramic for low-noise operation |
| REFCOMP (4) | Reference compensation node | Stabilizes internal reference amplifier; requires 47µF tantalum + 0.1µF ceramic bypass |
| AGND (5–8) | Analog ground terminals | Multiple low-inductance connections to analog ground plane minimize noise coupling into sampling circuitry |
| DVDD (9), DGND (10) | Digital logic supply and ground | Isolates digital switching noise from analog section; decoupled with 10µF + 0.1µF |
| D15–D0 (11–26) | 16-bit parallel output bus | Three-state outputs compatible with 3V or 5V systems via dedicated OVDD pin (29) |
| BUSY (27) | Conversion status indicator | Active-low signal; rising edge marks valid data ready for latching |
| OGND (28), OVDD (29) | Output driver ground and supply | Separate power domain isolates output switching transients from core logic |
| RD (30) | Read strobe input | Enables output drivers when CS is low; controls data access timing per t10 (40–75ns) |
| CONVST (31) | Conversion start trigger | Falling-edge initiated; minimum pulse width 40ns; critical timing window avoids DNL degradation |
| CS (32) | Chip select | Must be low to enable CONVST and RD recognition; selects nap/sleep shutdown mode with SHDN |
| SHDN (33) | Power shutdown control | Low-active; CS state determines Nap (CS low) or Sleep (CS high) mode |
| VSS (34) | Negative supply (–5V) | Decoupled with 10µF tantalum + 0.1µF ceramic; absolute max –6V |
| AVDD (35–36) | Analog positive supply (5V) | Dual pins reduce IR drop; connected via 10Ω resistor for improved PSRR |
Key Features
| Feature | Design Value |
|---|---|
| No pipeline delay | Successive-approximation architecture delivers conversion result immediately after BUSY rises - eliminates latency-critical buffering in real-time control loops |
| True differential input with 68dB CMRR | Rejects common-mode noise up to 15MHz, enabling accurate measurements in electrically noisy industrial environments without external instrumentation amplifiers |
| Two-tier shutdown (Nap/Sleep) | Nap mode retains reference and logic bias for 200ns wake-up; Sleep mode reduces current to 1µA for battery-powered idle periods |
| µP-compatible parallel interface | CS/CONVST/RD timing aligns with standard microprocessor memory-mapped I/O cycles - no custom glue logic required |
| Internal 2.5V reference with 15ppm/°C tempco | Meets precision DC accuracy requirements (±0.125% full-scale error) without external reference components or calibration |
| Pin compatibility with LTC1604/LTC1608 | Enables drop-in migration between 16-bit/14-bit/12-bit variants within same footprint - simplifies design reuse and BOM rationalization |
Applications
| Telecommunications Baseband Processing | Digital Signal Processing Systems |
|---|---|
Use Scenario: Digitizing IF signals in cellular base station receivers prior to FPGA-based demodulation. IC Role / Device Role / Timing Role: High-fidelity ADC front-end capturing 5MHz bandwidth signals with 90dB SINAD to preserve EVM in QAM-64/256 constellations. Use Value: 5MHz full-power bandwidth and –100dB THD ensure minimal distortion of adjacent channel interference during multi-carrier processing. | Use Scenario: Real-time spectral analysis in portable vibration analyzers using FFT-based algorithms. IC Role / Device Role / Timing Role: Sampling sensor outputs at 250ksps with no missing codes to maintain integrity of frequency-domain bin resolution. Use Value: Guaranteed monotonicity and 350kHz linear bandwidth enable accurate amplitude tracking across harmonics up to 175kHz. |
| Multiplexed Data Acquisition Systems | Imaging Systems |
Use Scenario: High-channel-count medical EEG systems requiring synchronized sampling across 64+ electrodes. IC Role / Device Role / Timing Role: Standalone ADC per channel with Nap-mode power cycling to manage thermal density in compact enclosures. Use Value: 7mW Nap mode cuts total system power by >90% during inter-sample intervals while maintaining sub-µs wake-up readiness. | Use Scenario: Industrial X-ray detector readout where low noise and linearity determine image contrast resolution. IC Role / Device Role / Timing Role: Converting photodiode array outputs with ±2.5V range to preserve dynamic range from dark current to saturation. Use Value: ±0.125% full-scale error and <1LSB INL ensure pixel-level grayscale fidelity without per-sensor calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8860IDRCT | 16-bit, 1MSPS, single-ended input only; requires external reference; 1.8V/3.3V supply | Lacks differential input and internal reference - needs additional op-amps and reference ICs for equivalent functionality | Select when higher speed justifies added BOM complexity and board area for external support components |
| LTC2378-16IUK#PBF | 16-bit, 1MSPS, differential input, internal reference; 3.3V supply only; no Nap/Sleep modes | Higher speed but incompatible ±5V supply requirement and lacks low-power shutdown states | Choose for 1MSPS applications where ±5V rails are unavailable and continuous operation is acceptable |
Compared with ADS8860IDRCT and LTC2378-16IUK#PBF, the LTC1603CG#TRPBF uniquely combines ±5V operation, integrated reference, differential inputs, and dual low-power modes in a pin-compatible 36-SSOP package - making it optimal for legacy industrial designs requiring drop-in replacement with minimal layout change.
Availability
LTC1603CG#TRPBF is available at Aetrix Electronics and suitable for telecommunications baseband processing, digital signal processing systems, and multiplexed data acquisition systems requiring stable component supply across extended production lifecycles.
Supply support for LTC1603CG#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC1603CG#TRPBF belongs to ADI's legacy Linear Technology precision data acquisition product line, engineered for high-speed, low-noise, and low-power applications in test equipment, medical instrumentation, and industrial control systems.
FAQ
What is the operating temperature range for the LTC1603CG#TRPBF?
The LTC1603CG#TRPBF is rated for commercial-grade operation from 0°C to 70°C. This is indicated by the "G" suffix in the part number and confirmed in the Absolute Maximum Ratings table, where LTC1603C specifies exactly this range. The device guarantees full performance - including no missing codes, ±3LSB integral linearity, and 90dB S/(N+D) - across this entire span without derating.
Does the LTC1603CG#TRPBF require an external clock source?
No, the LTC1603CG#TRPBF does not require an external clock. It contains a fully integrated, factory-trimmed internal clock that delivers a guaranteed maximum conversion time of 3.8µs and supports the full 250ksps sampling rate. The internal clock eliminates timing jitter from external sources and removes the need for clock distribution circuitry, simplifying PCB layout and reducing BOM count.
How does the Nap mode differ from Sleep mode in the LTC1603CG#TRPBF?
In Nap mode (SHDN low, CS low), the LTC1603CG#TRPBF disables the analog front-end and sampling circuitry while retaining bias on the internal reference and digital logic, drawing 7mW and waking in 200ns. In Sleep mode (SHDN low, CS high), all active bias currents are shut down, reducing power to 10µW but requiring longer wake-up time - up to 160ms - due to reference settling. The LTC1603CG#TRPBF uses these distinct states to optimize trade-offs between latency and ultra-low-power standby.
Can the LTC1603CG#TRPBF interface directly with a 3V microprocessor?
Yes, the LTC1603CG#TRPBF can interface directly with 3V microprocessors. Its digital inputs (SHDN, CS, CONVST, RD) accept 3V logic levels, and its outputs (D15–D0, BUSY) are driven from a separate OVDD pin (Pin 29) - allowing OVDD to be set to 3V for full 3V-compatible signaling. This eliminates level-shifters and ensures reliable communication with modern low-voltage controllers without signal integrity compromise.
What is the purpose of the REFCOMP pin (Pin 4) on the LTC1603CG#TRPBF?
The REFCOMP pin (Pin 4) on the LTC1603CG#TRPBF is the compensation node for the internal reference amplifier, which buffers and gains the 2.5V bandgap reference to generate the 4.375V voltage needed by the capacitive DAC. It must be bypassed to AGND with a minimum 22µF capacitor - typically 47µF tantalum in parallel with 0.1µF ceramic - to ensure stability and low-noise operation. Omitting this bypass causes reference instability and degraded AC performance.
LTC1603CG#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 250k
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- ±5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 36-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1603CG#TRPBF FAQ
1.How can I place an order for LTC1603CG#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1603CG#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1603CG#TRPBF reliable?
The price and inventory of LTC1603CG#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1603CG#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC1603CG#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1603CG#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1603CG#TRPBF?
LTC1603CG#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1603CG#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1603CG#TRPBF?
For technical support, including LTC1603CG#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1603CG#TRPBF requirements.
6.How does Aetrix verify that LTC1603CG#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC1603CG#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1603CG#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC1603CG#TRPBF?
All LTC1603CG#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1603CG#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1603CG#TRPBF part is unused and in its original packaging.
Return procedure for LTC1603CG#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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