Analog Devices Inc. LTC1609CG#PBF

Overview

LTC1609CG#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 200ksps serial analog-to-digital converter with integrated sample-and-hold, precision 2.5V reference, and internal clock. It supports ±10V, ±5V, ±3.3V bipolar and 0V–10V, 0V–5V, 0V–4V unipolar input ranges, delivers ±2LSB INL and 87dB typical SNR, and operates from a single 5V supply drawing 65mW. It is used in high-speed industrial data acquisition systems requiring stable DC accuracy and low noise.

For engineers reviewing the LTC1609CG#PBF datasheet, LTC1609CG#PBF pinout, LTC1609CG#PBF application, or LTC1609CG#PBF equivalent, key selection considerations include guaranteed no missing codes over temperature, support for both internal and external reference configurations, flexible serial interface timing (internal/external DATACLK), and dual ground separation (AGND1/AGND2/DGND) for mixed-signal noise isolation.

Technical Context

The LTC1609CG#PBF employs a switched-capacitor successive approximation architecture with auto-zeroed comparator and 16-bit capacitive DAC. Its conversion cycle includes a 2µs acquisition phase followed by a 3µs conversion time, achieving full 5µs throughput. The device uses separate analog (AGND1, AGND2) and digital (DGND) ground pins to minimize coupling between sampling circuitry and serial output logic.

It features dual reference options: internal 2.5V bandgap reference (±5ppm/°C tempco, 2.47–2.52V) or external reference (2.3–2.7V), with REF and CAP pins providing buffered and unbuffered outputs respectively. Input range selection is configured via resistor networks on R1IN/R2IN/R3IN, enabling six standard ranges without external op-amps.

Key Specifications

Pinout & Package

Package: 28-pin SSOP (G package), 5.6mm × 10.2mm body, 0.65mm pitch, RoHS-compliant lead-free finish (Pb-free plating per #PBF suffix).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit serial ADC applications.

Compared with ADS7809U and AD977ARZ, the LTC1609CG#PBF uniquely combines 200ksps throughput, integrated 2.5V reference, and flexible clocking (internal/external DATACLK), making it optimal for new high-speed industrial DAQ designs where board space and BOM count are constrained.

Availability

LTC1609CG#PBF is available at Aetrix Electronics and suitable for industrial process control, multiplexed data acquisition systems, and high-speed PC-based DAQ requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LTC1609CG#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LTC1609CG#PBF belongs to Linear Technology's precision data acquisition product line, designed specifically for high-resolution, medium-speed industrial and instrumentation applications where DC accuracy, noise performance, and ease of integration outweigh ultra-high-speed requirements.

FAQ

What input voltage ranges does the LTC1609CG#PBF support?

The LTC1609CG#PBF supports six factory-specified input ranges: bipolar ±10V, ±5V, ±3.3V and unipolar 0V–10V, 0V–5V, 0V–4V. Range selection is accomplished by connecting R1IN, R2IN, and R3IN to AGND, VIN, or CAP through specified resistors (e.g., 200Ω/100Ω networks). Each range has defined nominal input impedance (e.g., 22.9kΩ for ±10V), and all inputs tolerate ±25V fault conditions without damage. The LTC1609CG#PBF does not support software-selectable ranges - configuration is strictly hardware-based via external resistors.

How does the LTC1609CG#PBF handle reference voltage options?

The LTC1609CG#PBF integrates a factory-trimmed 2.500V ±15mV bandgap reference with ±5ppm/°C tempco. REF provides the raw reference output; CAP supplies the buffered version, both requiring 2.2µF tantalum bypassing. An external reference (2.3V–2.7V) may overdrive REF to improve absolute accuracy, but doing so disables the internal reference and requires external decoupling. The LTC1609CG#PBF's full-scale range scales linearly with VREF, so external references directly impact LSB size and input range boundaries.

What is the purpose of the SB/BTC and EXT/INT pins on the LTC1609CG#PBF?

SB/BTC configures serial output format: high = straight binary (0x0000 to 0xFFFF for 0V–10V), low = two's complement (0x8000 to 0x7FFF for ±10V). EXT/INT selects clock source: high = external DATACLK drives serial output (enabling daisy-chaining), low = internal clock pulses DATACLK and shifts data automatically. These pins are static controls - set once at power-up - and determine fundamental interface behavior of the LTC1609CG#PBF, affecting firmware design and PCB routing.

Can the LTC1609CG#PBF be used in power-constrained applications?

Yes. The LTC1609CG#PBF includes a PWRD pin that reduces supply current to 10µA typical (50µW dissipation) when asserted high. In this mode, the internal reference and clock are disabled, but the last conversion result remains latched in the output shift register for readout. Recovery time depends on external capacitor recharge; using the recommended 2.2µF on CAP and REF ensures <100µs wake-up. This makes the LTC1609CG#PBF suitable for battery-backed data loggers or intermittent-sampling systems.

What are the grounding requirements for optimal performance of the LTC1609CG#PBF?

The LTC1609CG#PBF requires three isolated ground connections: AGND1 (sample-and-hold section), AGND2 (reference buffer), and DGND (digital I/O). All must connect to a common system ground point *only* at the ADC's ground plane star point - not at the power supply or elsewhere. Separating AGND1 and AGND2 prevents reference buffer noise from modulating the sampling node, preserving ±2LSB INL. DGND must be routed away from analog traces and tied to AGND planes only at the designated star point to avoid digital switching noise coupling into analog paths.