Analog Devices Inc. LTC1740IG#PBF
- Part No.:
- LTC1740IG#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 36-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC1740IG#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 36SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,667
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Product details
Overview
LTC1740IG#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 6 Msps pipelined analog-to-digital converter with differential input architecture, ±2.5V full-scale range using internal 4.5V reference, 79 dB S/(N+D) at 2.5 MHz input, and 80 MHz full-power bandwidth - deployed in high-speed spectral analysis and telecommunications data acquisition systems.
For engineers reviewing the LTC1740IG#PBF datasheet, LTC1740IG#PBF pinout, LTC1740IG#PBF application, or LTC1740IG#PBF equivalent, key selection criteria include guaranteed no missing codes over temperature, 75 dB common-mode rejection for ground-loop mitigation, dual ±5V or single 5V supply operation, and 3V–5V output logic compatibility via OVDD pin.
Technical Context
The LTC1740IG#PBF implements a fully differential sample-and-hold front-end followed by a 14-bit pipelined CMOS ADC core with digital correction logic. Its timing architecture features fixed 100 ns conversion time and 3-cycle pipeline latency, where output data becomes valid on the third rising CLK edge after sampling.
It supports flexible reference configuration: SENSE pin selects between 4.5 V (±2.5 V input range), 2.25 V (±1.25 V), or external reference drive mode. Input common-mode voltage is arbitrary within supply rails, and VCM pin provides a buffered 2.5 V reference for single-supply biasing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with guaranteed no missing codes over –40°C to +85°C |
| Sampling Rate | 6 Msps maximum - supports real-time digitization of signals up to 3 MHz Nyquist bandwidth |
| S/(N+D) | 79.0 dB at 2.5 MHz input - defines usable dynamic range for RF/IF signal capture |
| SFDR | 91 dB at 2.5 MHz input - enables detection of low-level spurs in spectral analysis |
| INL / DNL | ±2.5 LSB max INL, ±1.25 LSB max DNL - ensures monotonicity and precision in control loop feedback |
| Power Dissipation | 245 mW typical at 6 Msps - enables thermal management in dense mixed-signal PCB layouts |
| Full-Power Bandwidth | 80 MHz - allows accurate sampling of fast transients and wideband modulated signals |
Pinout & Package
Package: 36-lead plastic SSOP (0.209-inch width), RoHS-compliant, moisture-sensitive level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| +AIN (1) | Differential analog input positive | Accepts true differential or single-ended input; high-Z during hold, draws charge spike at acquisition |
| –AIN (2) | Differential analog input negative | Paired with +AIN; common-mode rejection enabled only when both pins driven differentially |
| VCM (3) | 2.5 V reference output | Low-impedance buffered source for single-supply input biasing; requires ≥1 µF ceramic bypass |
| SENSE (4) | Reference programming control | GND = 4.5 V VREF (±2.5 V range); VREF = 2.25 V VREF (±1.25 V); VDD = external reference mode |
| VREF (5) | ADC reference voltage input | Set to ±VREF/1.8 full-scale range; 1 kΩ input impedance; bypass with ≥1 µF ceramic capacitor |
| GND (6,7,10,31,34) | Analog power ground | Must connect to dedicated analog ground plane; separate from digital ground except at OGND |
| VDD (8,9,32,33) | +5 V analog supply | Four independent pins; each requires individual 1–10 µF ceramic bypass to GND |
| OGND (11,28) | Output logic ground | Reference for OVDD domain; tie to system digital ground at single point near Pin 28 |
| D13–D0 (12–18,20–26) | 14-bit two's complement parallel output | D13 = MSB, D0 = LSB; outputs valid 3 cycles after CLK rising edge; slew rate controlled by OVDD |
| CLK (35) | Conversion start clock | Rising-edge triggered; 5 ns max rise time recommended for <0.6 psRMS aperture jitter |
| BUSY (27) | Conversion status indicator | Active-low during conversion; rising edge indicates data ready for latching on next CLK |
| OF (36) | Overflow flag | High when output = 01111111111111 or 10000000000000 - enables real-time clipping detection |
| VSS (29,30) | Negative supply | –5 V (dual supply) or 0 V (single supply); bypass with 1 µF ceramic if not tied to GND |
| OVDD (19) | Output logic supply | 2.7 V to 5.25 V - sets output voltage levels and drive strength for interfacing to 3 V or 5 V logic |
Key Features
| Feature | Design Value |
|---|---|
| True differential input with 75 dB CMRR | Enables noise-immune measurement of floating or ground-referenced signals without external instrumentation amps |
| Programmable reference via SENSE pin | Supports ±2.5 V, ±1.25 V, or user-defined input ranges - eliminates external resistor networks for gain scaling |
| 3-cycle deterministic pipeline latency | Allows precise timing alignment in synchronous systems such as digital downconverters and real-time controllers |
| Internal 2.5 V VCM reference output | Provides stable bias for single-supply sensor interfaces or op-amp drivers - reduces BOM count and layout area |
| Out-of-range (overflow) flag | Hardware-level saturation detection without software polling - critical for closed-loop protection and adaptive gain control |
Applications
| Telecommunications Baseband Digitization | Multiplexed Data Acquisition Systems |
|---|---|
Use Scenario: Digitizing I/Q baseband signals from quadrature demodulators in wireless infrastructure equipment operating at 2–5 MHz IF. IC Role / Device Role / Timing Role: High-fidelity 14-bit ADC capturing dual-channel complex waveforms at 6 Msps with synchronized BUSY/CLK timing. Use Value: 79 dB S/(N+D) and 91 dB SFDR preserve EVM and adjacent channel leakage ratio (ACLR) in LTE/5G transceivers. | Use Scenario: Simultaneous sampling of multiple sensor channels (e.g., vibration, temperature, strain) in industrial PLC modules. IC Role / Device Role / Timing Role: Central ADC in time-interleaved or multiplexed architecture, leveraging OF flag for automatic range adaptation per channel. Use Value: ±2.5 V bipolar input range and 75 dB CMRR reject ground-bounce noise across distributed sensor harnesses. |
| High-Speed Spectral Analysis | Imaging System Signal Chain |
Use Scenario: Real-time 4096-point FFT processing of RF spectrum for EMC testing or cognitive radio sensing. IC Role / Device Role / Timing Role: Front-end digitizer feeding FPGA-based FFT engine; uses deterministic 3-cycle latency for pipeline synchronization. Use Value: 80 MHz full-power bandwidth captures harmonics up to 5th order without aliasing in 2.5 MHz fundamental measurements. | Use Scenario: Digitizing CCD/CMOS line-scan sensor outputs in medical X-ray or industrial inspection cameras. IC Role / Device Role / Timing Role: Low-noise, DC-accurate ADC accepting differential pixel signals with programmable gain via VREF scaling. Use Value: <1 LSB INL and no missing codes ensure pixel intensity linearity across full temperature range (–40°C to +85°C). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9240ASTZ-80 | 14-bit, 80 Msps; higher speed but 3× higher power (750 mW); LVDS outputs vs parallel CMOS | Requires FPGA with LVDS receivers; unsuitable for microcontroller direct interface | Select when >6 Msps throughput or JESD204B/LVDS interface is required |
| MAX1186ECM+ | 14-bit, 3 Msps; lower speed, 1.8 V/3.3 V supply only; no internal reference or VCM output | Lacks SENSE-programmable range and 2.5 V bias - needs external reference circuitry | Select for battery-powered portable instruments where 3 Msps suffices and supply voltage is constrained |
Compared with AD9240ASTZ-80 and MAX1186ECM+, the LTC1740IG#PBF uniquely balances 6 Msps throughput, integrated reference flexibility, and 3V–5V logic compatibility - making it optimal for cost-sensitive, space-constrained industrial and telecom boards requiring minimal support components.
Availability
LTC1740IG#PBF is available at Aetrix Electronics and suitable for telecommunications baseband digitization, multiplexed industrial data acquisition, and high-speed spectral analysis requiring stable component supply across extended temperature ranges.
Supply support for LTC1740IG#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC1740IG#PBF belongs to ADI's legacy Linear Technology high-speed precision ADC product line, designed specifically for applications demanding wide bandwidth, excellent AC performance, and simplified analog front-end integration in compact PCB layouts.
FAQ
What is the operating temperature range for the LTC1740IG#PBF?
The LTC1740IG#PBF is specified for industrial operation from –40°C to +85°C. This rating is confirmed in the Absolute Maximum Ratings table and applies to all guaranteed specifications including INL, DNL, S/(N+D), and SFDR. The "I" suffix explicitly denotes this extended temperature grade, distinguishing it from the commercial-grade LTC1740CG (0°C to 70°C). Thermal derating is not required within this range.
Does the LTC1740IG#PBF require an external clock driver for optimal performance?
Yes - for best AC performance, the LTC1740IG#PBF requires a low-jitter clock source with ≤5 ns rise time. The datasheet specifies that aperture jitter contributes directly to SNR degradation via SNR = –20log(2πfINtJ). A crystal oscillator or low-phase-noise PLL is recommended; logic gates may be used to sharpen slower clocks. The LTC1740IG#PBF itself does not include an on-chip PLL or clock conditioner.
Can the LTC1740IG#PBF operate from a single 3.3 V supply?
No - the LTC1740IG#PBF requires either a single 5 V analog supply (VDD = 5 V, VSS = 0 V) or dual ±5 V supplies (VDD = +5 V, VSS = –5 V). While OVDD supports 2.7 V to 5.25 V for digital output interfacing, the analog core mandates 5 V operation. Attempting 3.3 V on VDD violates Absolute Maximum Ratings and will result in undefined conversion behavior or damage.
How is the overflow flag (OF) used in real-time signal processing with the LTC1740IG#PBF?
The OF pin on the LTC1740IG#PBF asserts high when the input exceeds ±VREF/1.8 - corresponding to output codes 01111111111111 or 10000000000000. In real-time systems, OF can trigger hardware interrupts or feed back to AGC circuitry to adjust VREF via DAC (as shown in Figure 3b), enabling adaptive full-scale optimization without CPU intervention. It is asynchronous to CLK and valid immediately upon overflow detection.
Is the LTC1740IG#PBF pin-compatible with other members of the LTC1740 family?
Yes - all LTC1740 variants (including LTC1740CG, LTC1740IG, and LTC1740HG) share identical 36-pin SSOP packaging and pinout. The only differences are temperature grade (C/I/H) and associated screening/test limits. No PCB redesign is needed when upgrading from CG to IG grade, and all electrical interface requirements (bypassing, grounding, timing) remain unchanged.
LTC1740IG#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 6M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- ±5V, 5V
- Voltage - Supply, Digital:
- -
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 36-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1740IG#PBF FAQ
1.How can I place an order for LTC1740IG#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1740IG#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1740IG#PBF reliable?
The price and inventory of LTC1740IG#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1740IG#PBF is usually 5 days.
3.What payment methods are accepted for LTC1740IG#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1740IG#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1740IG#PBF?
LTC1740IG#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1740IG#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1740IG#PBF?
For technical support, including LTC1740IG#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1740IG#PBF requirements.
6.How does Aetrix verify that LTC1740IG#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1740IG#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1740IG#PBF meets industry standards.
7.What is the process for return or replacement of LTC1740IG#PBF?
All LTC1740IG#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1740IG#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1740IG#PBF part is unused and in its original packaging.
Return procedure for LTC1740IG#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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