Analog Devices Inc. LTC1743CFW#PBF

Overview

LTC1743CFW#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 50Msps pipelined analog-to-digital converter optimized for high-frequency, wide-dynamic-range signal digitization in communications systems. It features ±1V or ±1.6V differential input ranges, 72.5dB SNR at 3.2V range, 85dB SFDR, and ultralow 0.3psRMS aperture jitter - enabling undersampling of IF signals in cellular base stations and spectrum analyzers.

For engineers reviewing the LTC1743CFW#PBF datasheet, LTC1743CFW#PBF pinout, LTC1743CFW#PBF application, or LTC1743CFW#PBF equivalent, key selection criteria include its 48-pin TSSOP package with flow-through layout, resistor-programmable input range, differential ENC/ENC interface compatibility with PECL/GTL/TTL/CMOS, and separate OVDD supply (0.5V–5V) for direct interfacing with low-voltage DSPs or FIFOs.

Technical Context

The LTC1743CFW#PBF implements a four-stage CMOS pipelined ADC architecture with internal residue amplification and digital correction logic, delivering 12-bit resolution with no missing codes across temperature. Its sample-and-hold uses direct capacitor sampling (7pF CSAMPLE) and achieves 150MHz full-power bandwidth with 7.5ns acquisition time.

It supports dual reference configurations via the SENSE pin (ground = ±1V, VDD = ±1.6V), integrates a 2.5V VCM output with ±30ppm/°C tempco, and provides offset binary or 2's complement output format selectable via MSBINV. The ENC/ENC differential encode interface accepts sinusoidal drive without performance degradation.

Key Specifications

Pinout & Package

The LTC1743CFW#PBF is housed in a 48-lead plastic TSSOP (FW package) with flow-through pinout optimized for high-speed PCB layout and minimal trace coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9226ASTZ and LTC2245IUP#PBF, the LTC1743CFW#PBF uniquely balances 50Msps speed, 12-bit precision, ±1V/±1.6V programmability, and 0.5V–5V OVDD support - making it optimal for cost-sensitive, layout-constrained communications receivers where flexibility trumps raw resolution.

Availability

LTC1743CFW#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, test equipment, and imaging systems requiring stable component supply, long-term obsolescence management, and consistent parametric performance across production lots.

Supply support for LTC1743CFW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving aerospace, communications, industrial, and medical markets.

The LTC1743CFW#PBF belongs to ADI's legacy Linear Technology high-speed ADC product line, engineered specifically for demanding communications infrastructure applications requiring low jitter, wide input bandwidth, and flexible interface voltage scaling.

FAQ

What input voltage ranges does the LTC1743CFW#PBF support, and how are they selected?

The LTC1743CFW#PBF supports two differential input ranges: ±1V and ±1.6V. Selection is made via the SENSE pin - grounding SENSE selects ±1V, connecting SENSE to VDD selects ±1.6V. Intermediate voltages between 1V and 1.6V scale the range proportionally (e.g., 1.3V yields ±1.3V). This resistor-programmable feature allows optimization for varying front-end gain without redesigning the signal chain. The LTC1743CFW#PBF datasheet specifies full AC performance across both ranges.

Does the LTC1743CFW#PBF require external reference components, and what is the role of the VCM pin?

No, the LTC1743CFW#PBF integrates an internal 2.5V bandgap reference and differential reference buffer - only external bypass capacitors (4.7µF on REFHA/REFLA, 0.1µF on REFLB/REFHB) are required. The VCM pin provides a buffered 2.5V common-mode output with ±30ppm/°C tempco, intended to bias transformer center-taps or op-amp VOCM inputs. It must be bypassed to AGND with ≥4.7µF ceramic capacitance per the LTC1743CFW#PBF layout guidelines.

How does the ENC/ENC differential interface operate, and can it accept single-ended signals?

The ENC and ENC pins form a true differential encode input that triggers conversion on the ENC-to-ENC transition. For single-ended use, ENC is driven with the clock signal while ENC is bypassed to ground via 0.1µF. The LTC1743CFW#PBF's low-noise, high-gain ENC/ENC receivers also accept sinusoidal drive directly - eliminating need for clock conditioning circuitry. Timing parameters (t1, t2) are specified for both differential and single-ended modes in the LTC1743CFW#PBF datasheet.

What is the purpose of the OVDD supply, and what voltage range is supported?

The OVDD supply powers only the digital output drivers (D0–D11, CLKOUT, OF), decoupling them from the analog VDD domain. It supports 0.5V to 5V, enabling direct interfacing with 1.8V, 2.5V, 3.3V, or 5V logic families without level shifters. This separation minimizes digital switching noise coupling into analog sections. The LTC1743CFW#PBF specifies VOH/VOL and timing (t4, t5, t6) across the full OVDD range, ensuring robust operation in mixed-voltage systems.

Is the LTC1743CFW#PBF pin-compatible with other members of the LTC174x family, and which variants share the same footprint?

Yes, the LTC1743CFW#PBF is pin-compatible with the entire LTC174x family in the 48-pin TSSOP (FW) package, including LTC1741, LTC1742, LTC1744, LTC1745, LTC1746, LTC1747, and LTC1748. All share identical pinout, power sequencing, and interface signaling - allowing drop-in upgrades (e.g., LTC1743CFW#PBF → LTC1744CFW#PBF for 14-bit resolution) or downgrades without PCB revision. This compatibility is explicitly confirmed in the LTC1743CFW#PBF datasheet's "Pin Compatible Family" section.