Analog Devices Inc. LTC1745IFW#PBF
- Part No.:
- LTC1745IFW#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
LTC1745IFW#PBF.pdf
- Description:
- IC ADC 12BIT PIPELINED 48TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:156
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC1745IFW#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 25 Msps pipelined analog-to-digital converter optimized for high-frequency, wide dynamic range signal digitization in communications and instrumentation systems. It delivers 72.5 dB SNR and 91 dB SFDR at 3.2 V input range, operates from a single 5 V supply, and features ±1 V or ±1.6 V differential analog input range selection via the SENSE pin.
For engineers reviewing the LTC1745IFW#PBF datasheet, LTC1745IFW#PBF pinout, LTC1745IFW#PBF application, or LTC1745IFW#PBF equivalent, key selection criteria include its 240 MHz full-power bandwidth, 0.3 psRMS aperture jitter, ±1 LSB INL max over temperature, flow-through TSSOP-48 layout compatibility, and dual-voltage digital I/O support (0.5 V to 5 V OVDD).
Technical Context
The LTC1745IFW#PBF implements a 4-stage CMOS pipelined ADC architecture with integrated sample-and-hold, internal 2.35 V bandgap reference, and programmable differential input range. Its differential ENC/ENC encode interface accepts PECL, GTL, TTL, or sinusoidal drive, enabling low-jitter sampling critical for undersampling applications.
DC accuracy is specified across temperature: ±1 LSB integral nonlinearity and ±0.75 LSB differential nonlinearity over –40°C to +85°C. The digital output drivers support independent OVDD (0.5 V to 5 V), allowing direct interfacing with low-voltage DSPs or FIFOs without level-shifting circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonic transfer function for precision measurement. |
| Sampling Rate | 25 Msps - supports Nyquist-limited bandwidth up to 12.5 MHz; enables real-time baseband digitization in IF-sampling receivers. |
| SNR / SFDR | 72.5 dB / 91 dB at 5 MHz, 3.2 V range - defines usable dynamic range for high-fidelity signal capture in spectrum analysis. |
| Aperture Jitter | 0.3 psRMS - limits sampling-time uncertainty, enabling <73 dB SNR at 100 MHz input frequency per jitter-limited SNR formula. |
| Input Range | Selectable ±1 V or ±1.6 V differential - configurable via SENSE pin tied to GND or VDD, optimizing SNR/SFDR trade-off per application frequency. |
| INL / DNL | ±1 LSB / ±0.75 LSB max over –40°C to +85°C - ensures accurate amplitude fidelity in medical imaging and test equipment calibration paths. |
| Power Dissipation | 380 mW at 25 Msps, 2 V range - enables thermal management in dense RF front-end PCB layouts without forced air cooling. |
Pinout & Package
The LTC1745IFW#PBF is housed in a 48-lead plastic TSSOP (FW package) with flow-through pinout designed to minimize trace crossovers and simplify high-speed analog/digital partitioning on PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN+, AIN– | Differential analog input | Accepts ±1 V or ±1.6 V swing centered at 2.35 V common-mode; requires matched 50 Ω source impedance for optimal SFDR. |
| SENSE | Input range select | GND = ±1 V range; VDD = ±1.6 V range; intermediate voltage sets proportional range - enables application-specific dynamic range tuning. |
| VCM | Common-mode bias output | 2.35 V buffered reference; must be bypassed with ≥4.7 µF ceramic capacitor to ground for stability and noise rejection. |
| ENC, ENC | Differential encode clock input | Accepts PECL/GTL/sinusoidal signals; conversion starts on ENC rising edge; low jitter critical for undersampling performance. |
| D0–D11 | 12-bit parallel digital output | LSB-to-MSB outputs; OE-controlled tri-state; OVDD-supplied (0.5 V–5 V) - allows direct connection to 1.8 V, 2.5 V, or 3.3 V logic interfaces. |
| CLKOUT | Data valid strobe | Rising edge indicates stable data on D0–D11; synchronized to internal pipeline latency (5 cycles), enabling deterministic timing alignment. |
| OF | Over/underflow flag | Active-high pulse indicates input exceeded selected full-scale range - enables real-time clipping detection in receiver AGC loops. |
Key Features
| Feature | Design Value |
|---|---|
| Flow-through TSSOP-48 pinout | Enables straight-layer routing of analog inputs, digital outputs, and power domains - reduces crosstalk and simplifies layout in high-density RF boards. |
| Resistor-programmable input range | Supports custom ranges between ±1 V and ±1.6 V using external resistors on SENSE pin - extends flexibility beyond binary selection for optimized system SNR. |
| Independent OVDD supply | 0.5 V to 5 V digital output rail - eliminates need for external level shifters when interfacing with ultra-low-voltage processors or memory buffers. |
| Ultralow 0.3 psRMS aperture jitter | Preserves SNR at high input frequencies (e.g., >50 MHz) - essential for direct RF sampling and wideband spectrum monitoring applications. |
| Internal 2.35 V bandgap reference | Stable, low-drift reference with ±30 ppm/°C tempco - provides precise common-mode bias and reference scaling without external components. |
Applications
| Telecommunications Base Stations | Medical Ultrasound Imaging |
|---|---|
|
Use Scenario: Digitizing IF signals in multi-carrier WCDMA/LTE transceivers operating at 70–150 MHz. IC Role / Device Role / Timing Role: High-speed ADC capturing 14-bit-equivalent dynamic range via oversampling; CLKOUT synchronizes FPGA-based digital downconversion. Use Value: 91 dB SFDR at 30 MHz input enables clean separation of adjacent channels in crowded spectral environments. |
Use Scenario: Beamforming channel digitization in portable ultrasound systems requiring compact, low-power signal acquisition. IC Role / Device Role / Timing Role: 12-bit pipeline ADC sampling echo return signals at 25 Msps; MSBINV configures offset binary output for real-time FPGA processing. Use Value: 380 mW power dissipation and TSSOP-48 footprint enable integration into handheld probe electronics with minimal thermal impact. |
| Spectrum Analyzers | Test & Measurement Receivers |
|
Use Scenario: Real-time FFT-based spectral monitoring across 0–12.5 MHz bandwidth with >70 dB spurious-free resolution. IC Role / Device Role / Timing Role: Primary digitizer in swept-tuned or vector signal analyzers; OF flag triggers automatic gain adjustment upon signal overload. Use Value: ±1 LSB INL ensures amplitude accuracy ≤0.025% FS across temperature - critical for calibrated power measurements. |
Use Scenario: High-fidelity signal capture in benchtop oscilloscopes and arbitrary waveform analyzers requiring low harmonic distortion. IC Role / Device Role / Timing Role: Front-end ADC with differential input and 240 MHz S/H bandwidth - preserves transient fidelity of fast-rising pulses and modulated waveforms. Use Value: 72.5 dB SNR at 5 MHz input supports ENOB ≈ 11.7 bits, meeting Class A instrument specifications per IEEE 1057. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9226ASTZ-RL7 | 12-bit, 65 Msps; higher speed but higher power (1.1 W); LVDS outputs only; no SENSE-range select. | Better suited for wideband IF sampling >25 MHz; requires LVDS termination and separate power rails. | Choose AD9226ASTZ-RL7 when sampling rate >25 Msps is mandatory and system can accommodate higher power and LVDS interface complexity. |
| LTC2245IUP#PBF | 14-bit, 25 Msps; improved SNR (75.5 dB) and SFDR (94 dB); same TSSOP-48 package; 3.3 V supply only. | Higher resolution for precision instrumentation; less flexible input range (fixed 2 Vpp differential). | Choose LTC2245IUP#PBF when 14-bit resolution and superior AC performance outweigh need for ±1 V/±1.6 V range configurability. |
Compared with AD9226ASTZ-RL7 and LTC2245IUP#PBF, the LTC1745IFW#PBF uniquely balances 25 Msps throughput, dual-range configurability, ultralow jitter, and single-supply 5 V operation - making it optimal for cost-sensitive, thermally constrained communications front-ends where design flexibility matters.
Availability
LTC1745IFW#PBF is available at Aetrix Electronics and suitable for telecommunications infrastructure, medical imaging systems, and test & measurement equipment requiring stable component supply across extended temperature ranges (–40°C to +85°C).
Supply support for LTC1745IFW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.
The LTC1745IFW#PBF belongs to Linear's legacy high-speed ADC family, engineered specifically for demanding communications and instrumentation applications requiring low jitter, excellent SFDR, and flexible input interface options.
FAQ
What is the operating temperature range for the LTC1745IFW#PBF?
The LTC1745IFW#PBF is rated for industrial operation from –40°C to +85°C (I-grade). This is confirmed by the "I" suffix in the part number and absolute maximum ratings table, which specifies TJMAX = 150°C and θJA = 35°C/W for the TSSOP-48 package. All DC and AC specifications - including ±1 LSB INL and 72.5 dB SNR - are guaranteed across this full range.
How does the SENSE pin configure the input range on the LTC1745IFW#PBF?
The SENSE pin on the LTC1745IFW#PBF selects full-scale input range: tying to GND sets ±1 V differential (2 Vpp), tying to VDD sets ±1.6 V differential (3.2 Vpp). Voltages between 1 V and 1.6 V program proportional ranges (e.g., 2.2 Vpp), enabling optimization of SNR vs. SFDR trade-offs per application frequency - a capability verified in the reference circuit diagrams and electrical characteristics tables.
Can the LTC1745IFW#PBF interface directly with a 1.8 V FPGA?
Yes. The LTC1745IFW#PBF supports OVDD from 0.5 V to 5 V, and its digital outputs (D0–D11, CLKOUT, OF) are fully specified down to 1.8 V OVDD per the Digital Inputs and Outputs table. VOH and VOL parameters are guaranteed at IO = ±200 µA, confirming robust 1.8 V logic compatibility without level shifters.
What is the data latency of the LTC1745IFW#PBF, and how is it synchronized?
The LTC1745IFW#PBF has a fixed 5-cycle pipeline latency from ENC edge to valid data on D0–D11, as stated in the Timing Characteristics table. CLKOUT provides a synchronous strobe aligned to this latency - its rising edge marks when output data is stable, enabling deterministic timing capture in FPGA or ASIC logic without additional delay compensation.
Does the LTC1745IFW#PBF require external reference components?
No external reference components are required for basic operation. The LTC1745IFW#PBF integrates a 2.35 V bandgap reference, differential reference buffers (REFHA/REFHB/REFLA/REFLB), and common-mode bias (VCM). Only mandatory external components are bypass capacitors: ≥4.7 µF on VCM, 1 µF on VDD, and 0.1 µF on REF pins - all specified in the Applications Information section.
LTC1745IFW#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 25M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 48-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1745IFW#PBF FAQ
1.How can I place an order for LTC1745IFW#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1745IFW#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1745IFW#PBF reliable?
The price and inventory of LTC1745IFW#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1745IFW#PBF is usually 5 days.
3.What payment methods are accepted for LTC1745IFW#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1745IFW#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1745IFW#PBF?
LTC1745IFW#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1745IFW#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1745IFW#PBF?
For technical support, including LTC1745IFW#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1745IFW#PBF requirements.
6.How does Aetrix verify that LTC1745IFW#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1745IFW#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1745IFW#PBF meets industry standards.
7.What is the process for return or replacement of LTC1745IFW#PBF?
All LTC1745IFW#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1745IFW#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1745IFW#PBF part is unused and in its original packaging.
Return procedure for LTC1745IFW#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC1745IFW#PBF Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

