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Analog Devices Inc. LTC1746CFW#PBF
- Part No.:
- LTC1746CFW#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
LTC1746CFW#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,963
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Product details
Overview
LTC1746CFW#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 25 Msps pipelined analog-to-digital converter optimized for high-frequency, wide dynamic range signal digitization in communications and instrumentation systems. It delivers 77.5 dB SNR and 91 dB SFDR at 3.2 V input range, operates from a single 5 V supply, and features ±1 V or ±1.6 V pin-selectable differential input ranges with 240 MHz full-power bandwidth.
For engineers reviewing the LTC1746CFW#PBF datasheet, LTC1746CFW#PBF pinout, LTC1746CFW#PBF application, or LTC1746CFW#PBF equivalent, key selection considerations include its 0.3 psRMS aperture jitter, ±3 LSB INL, no missing codes over temperature, flow-through TSSOP-48 layout, and compatibility with 5 V / 3 V / 2 V logic interfaces - critical for undersampling receivers and high-fidelity data acquisition.
Technical Context
The LTC1746CFW#PBF implements a four-stage CMOS pipelined ADC architecture with digital correction logic, achieving 5-cycle latency and supporting differential ENC/ENC encode timing. Its sample-and-hold uses direct capacitor sampling with 4 pF input capacitance and 15–18 ns acquisition time, enabling stable operation up to 70 MHz input frequency.
Internal reference generation includes a 2.35 V bandgap source, programmable ±1 V / ±1.6 V differential input ranges via SENSE pin control, and separate OVDD (0.5–5 V) for output drivers - allowing direct interfacing with low-voltage DSPs or FIFOs without level-shifting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with guaranteed no missing codes over 0°C to 70°C operating range |
| Sampling Rate | 25 Msps - fixed rate; supports undersampling of RF signals up to Nyquist (12.5 MHz) or beyond via aliasing |
| SNR / SFDR | 77.5 dB / 91 dB at 5 MHz, 3.2 V range - enables high-fidelity baseband digitization in spectrum analyzers |
| Aperture Jitter | 0.3 psRMS - limits SNR degradation to <0.1 dB at 70 MHz input, essential for wideband receiver performance |
| INL / DNL | ±3 LSB / ±1 LSB max - ensures accurate amplitude fidelity in medical imaging and test equipment waveforms |
| Input Bandwidth | 240 MHz full-power - supports direct sampling of IF signals up to 100+ MHz with minimal attenuation |
| Power Dissipation | 390 mW at 2 V range - enables thermally constrained board layouts in dense telecom modules |
Pinout & Package
Package: 48-lead plastic TSSOP (FW), 7.6 mm × 12.5 mm, 0.5 mm pitch, flow-through pinout optimized for signal integrity and minimal trace crossovers.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN+, AIN− | Differential analog input | Accepts ±1 V or ±1.6 V differential signal; requires 2.35 V common-mode bias (VCM) for optimal linearity |
| SENSE | Input range select | GND = ±1 V range; VDD = ±1.6 V range; intermediate voltage sets proportional range (e.g., 1.1 V → ±2.2 V) |
| VCM | Common-mode reference output | 2.35 V buffered output; must be bypassed with ≥4.7 µF ceramic capacitor to ground for stability and noise rejection |
| ENC, ENC | Differential encode clock inputs | Accept PECL/GTL/TTL/CMOS or sinusoidal drive; conversion triggered on ENC rising edge; 0.3 psRMS jitter preserved |
| D0–D13 | Parallel digital outputs | 14-bit offset binary or 2's complement (via MSBINV); OVDD supplies 0.5–5 V for direct interface to 1.8 V/2.5 V/3.3 V/5 V logic |
| CLKOUT | Data valid strobe | Rising edge indicates stable D0–D13 and OF outputs; synchronized to internal pipeline timing (5-cycle latency) |
| OF | Over/underflow flag | Active-high pulse indicates input exceeded selected full-scale range - enables real-time clipping detection |
Key Features
| Feature | Design Value |
|---|---|
| Pipe-lined 14-bit architecture | Delivers 25 Msps throughput with 5-cycle deterministic latency - simplifies timing closure in FPGA-based data capture systems |
| Programmable input range | Single-pin SENSE control selects ±1 V or ±1.6 V differential range - eliminates external gain-switching circuitry in multi-standard radios |
| Low-jitter sample-and-hold | 0.3 psRMS aperture jitter enables clean undersampling of 70 MHz IF signals without added noise floor elevation |
| Flexible digital interface | OVDD independently configurable from 0.5 V to 5 V - allows direct connection to low-voltage processors without level translators |
| Flow-through TSSOP-48 layout | Optimized pin assignment separates analog, digital, and power domains - reduces crosstalk and eases PCB routing |
Applications
| Telecommunications Base Stations | Medical Ultrasound Imaging |
|---|---|
|
Use Scenario: Digitizing 70 MHz IF signals in WCDMA/LTE radio transceivers using undersampling architecture. IC Role / Device Role / Timing Role: High-speed ADC front-end capturing wideband channelized signals with minimal distortion and jitter-induced noise. Use Value: 91 dB SFDR prevents adjacent-channel interference masking weak signals; 240 MHz bandwidth supports direct IF sampling without image-reject filtering. |
Use Scenario: Acquiring echo return signals from phased-array ultrasound probes with >12-bit dynamic range. IC Role / Device Role / Timing Role: Precision digitizer converting analog beamformed RF returns into digital samples for real-time B-mode processing. Use Value: 77.5 dB SNR preserves subtle tissue contrast; no missing codes ensures accurate grayscale rendering across full depth range. |
| Spectrum Analysis Equipment | High-Speed Data Acquisition Systems |
|
Use Scenario: Real-time FFT-based spectral monitoring in portable RF analyzers covering DC–100 MHz. IC Role / Device Role / Timing Role: Wideband ADC capturing instantaneous frequency domain snapshots with high spurious-free resolution. Use Value: 96 dB SFDR at 2 V range suppresses harmonic artifacts during multi-tone analysis; ±3 LSB INL maintains amplitude accuracy across sweep. |
Use Scenario: Capturing transient waveforms in automated test equipment for semiconductor validation. IC Role / Device Role / Timing Role: Low-latency digitizer synchronizing with precision trigger events and feeding high-speed memory buffers. Use Value: 5-cycle deterministic latency enables precise timestamp alignment; 390 mW power enables fanless enclosure design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9245BSTZ-25 | 14-bit, 25 Msps; 74 dB SNR, 88 dB SFDR; requires external reference; 3.3 V only digital interface | Lacks pin-selectable input range and internal 2.35 V VCM; lower SFDR limits multi-tone dynamic range | Choose when system already uses external reference and 3.3 V logic; avoid if ±1.6 V range or ultra-low jitter required |
| LTC2245IUP#PBF | 14-bit, 25 Msps; 75.5 dB SNR, 90 dB SFDR; 1.8 V digital interface; integrated dither; no SENSE pin range select | Fixed ±1.25 V input range; lower power (220 mW); no internal VCM output; different pinout | Prefer for battery-powered instruments needing lower power; not drop-in due to non-compatible pin mapping and range control |
Compared with AD9245BSTZ-25 and LTC2245IUP#PBF, the LTC1746CFW#PBF uniquely combines pin-selectable ±1 V/±1.6 V ranges, internal 2.35 V VCM output, and 0.3 psRMS jitter - making it optimal for compact, self-contained RF digitizers where layout simplicity and undersampling fidelity are critical.
Availability
LTC1746CFW#PBF is available at Aetrix Electronics and suitable for telecommunications infrastructure, medical imaging subsystems, and test & measurement equipment requiring stable component supply across extended production lifecycles.
Supply support for LTC1746CFW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.
The LTC1746CFW#PBF belongs to Linear's legacy high-speed ADC family designed specifically for demanding communications and instrumentation applications where dynamic range, jitter performance, and flexible interfacing are paramount.
FAQ
What is the operating temperature range for the LTC1746CFW#PBF?
The LTC1746CFW#PBF is specified for commercial-grade operation from 0°C to 70°C. This is indicated by the "C" suffix in the part number. The "I" grade variant (LTC1746IFW#PBF) extends to –40°C to +85°C. All AC and DC specifications in the datasheet marked with "G" apply across this full 0°C to 70°C range, including ±3 LSB INL and 77.5 dB SNR.
How does the SENSE pin configure the input range on the LTC1746CFW#PBF?
The SENSE pin on the LTC1746CFW#PBF directly selects the full-scale differential input range: tying SENSE to GND configures ±1 V, tying to VDD configures ±1.6 V, and applying a voltage between 1.0 V and 1.6 V sets a proportional range (e.g., 1.1 V → ±2.2 V). This eliminates external gain-setting resistors and enables rapid reconfiguration in multi-standard systems.
Can the LTC1746CFW#PBF interface directly with a 1.8 V FPGA?
Yes. The LTC1746CFW#PBF supports OVDD from 0.5 V to 5 V, so setting OVDD = 1.8 V configures D0–D13, CLKOUT, OE, and OF outputs for direct 1.8 V logic compatibility. No level shifters are needed, and the digital output drivers maintain specified VOH/VOL across this range per the datasheet's digital I/O characteristics table.
What is the purpose of the VCM pin on the LTC1746CFW#PBF?
The VCM pin on the LTC1746CFW#PBF provides a buffered 2.35 V common-mode reference output used to bias external differential drivers or transformer center taps. It must be bypassed with ≥4.7 µF ceramic capacitance to ground for stability and noise suppression. This internal bias eliminates the need for external precision references in most high-frequency signal chain designs.
Does the LTC1746CFW#PBF support both offset binary and 2's complement output formats?
Yes. The LTC1746CFW#PBF supports both formats via the MSBINV pin: logic high yields offset binary (0x0000 to 0x3FFF for ±1 V range), logic low inverts the MSB to produce 2's complement output. This flexibility simplifies integration with DSPs or FPGAs that expect either format without requiring post-processing bit manipulation.
LTC1746CFW#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 25M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 48-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC1746CFW#PBF FAQ
1.How can I place an order for LTC1746CFW#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1746CFW#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1746CFW#PBF reliable?
The price and inventory of LTC1746CFW#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1746CFW#PBF is usually 5 days.
3.What payment methods are accepted for LTC1746CFW#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1746CFW#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1746CFW#PBF?
LTC1746CFW#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1746CFW#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1746CFW#PBF?
For technical support, including LTC1746CFW#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1746CFW#PBF requirements.
6.How does Aetrix verify that LTC1746CFW#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1746CFW#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1746CFW#PBF meets industry standards.
7.What is the process for return or replacement of LTC1746CFW#PBF?
All LTC1746CFW#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1746CFW#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1746CFW#PBF part is unused and in its original packaging.
Return procedure for LTC1746CFW#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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