Analog Devices Inc. LTC1746IFW#PBF

Overview

LTC1746IFW#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 25 Msps pipelined analog-to-digital converter optimized for high-frequency, wide dynamic range signal digitization in communications and instrumentation systems. It delivers 77.5 dB SNR and 91 dB SFDR at 3.2 V input range, operates on a single 5 V supply, and features ±1 V or ±1.6 V differential input range selection via the SENSE pin.

For engineers reviewing the LTC1746IFW#PBF datasheet, LTC1746IFW#PBF pinout, LTC1746IFW#PBF application, or LTC1746IFW#PBF equivalent, key selection considerations include its 0.3 psRMS aperture jitter, 240 MHz full-power bandwidth, ±3 LSB INL, no missing codes over temperature, and TSSOP-48 flow-through pinout supporting direct interfacing to low-voltage DSPs and FIFOs.

Technical Context

The LTC1746IFW#PBF implements a four-stage CMOS pipelined ADC architecture with digital correction logic, achieving 5-cycle data latency and enabling undersampling of RF signals up to 70 MHz. Its differential analog input and encode interface suppress even-order harmonics and common-mode noise, while the internal 2.35 V bandgap reference drives both VCM bias and programmable reference buffers.

Input range selection (±1 V or ±1.6 V) is controlled by the SENSE pin voltage level, and the digital output drivers support independent OVDD from 0.5 V to 5 V - allowing seamless interfacing with 1.8 V, 2.5 V, or 3.3 V logic without level shifters. The ENC/ENC differential clock inputs accept PECL, GTL, TTL, or sinusoidal drive with ultralow jitter propagation.

Key Specifications

Pinout & Package

The LTC1746IFW#PBF is housed in a 48-lead plastic TSSOP (FW package) with flow-through pinout designed to minimize trace crossovers and simplify high-speed layout. Ground pins are distributed across multiple locations to reduce ground bounce and improve analog isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9245BCPZ-25 and LTC2245IUP#PBF, the LTC1746IFW#PBF uniquely integrates a 2.35 V VCM buffer, pin-selectable input range, and 0.3 psRMS jitter - reducing BOM count and improving undersampling SNR in compact telecom and instrumentation designs.

Availability

LTC1746IFW#PBF is available at Aetrix Electronics and suitable for telecommunications infrastructure, medical imaging equipment, and test & measurement instruments requiring stable component supply and long-term industrial temperature support (–40°C to +85°C).

Supply support for LTC1746IFW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing ICs for precision and high-speed applications.

The LTC1746IFW#PBF belongs to Linear's high-speed ADC product line, engineered specifically for demanding communications and instrumentation systems where dynamic range, jitter performance, and flexible input interfacing are critical.

FAQ

What is the operating temperature range for the LTC1746IFW#PBF?

The LTC1746IFW#PBF is rated for industrial operation from –40°C to +85°C, as indicated by the "I" grade suffix in the part number. This makes it suitable for base station radios, outdoor test equipment, and medical imaging systems exposed to extended ambient conditions. The device guarantees full specification compliance-including ±3 LSB INL and 77.5 dB SNR-across this entire range.

How does the SENSE pin configure the input range on the LTC1746IFW#PBF?

The SENSE pin on the LTC1746IFW#PBF selects the differential input full-scale range: tying SENSE to GND configures ±1 V range, connecting it to VDD selects ±1.6 V range, and applying an intermediate voltage (1.0 V to 1.6 V) scales the range linearly to ±V_SENSE. This eliminates external gain-switching circuitry and enables adaptive range optimization in multi-signal environments.

Can the LTC1746IFW#PBF interface directly with a 1.8 V FPGA?

Yes - the LTC1746IFW#PBF supports OVDD from 0.5 V to 5 V, so setting OVDD = 1.8 V enables direct, level-compatible connection to 1.8 V FPGA I/O banks without translators. Digital outputs D0–D13 and OF meet 1.8 V logic thresholds, and OE/CLKOUT/ENC inputs tolerate 1.8 V swing when VDD = 5 V, preserving timing margins.

What is the purpose of the VCM pin on the LTC1746IFW#PBF?

The VCM pin on the LTC1746IFW#PBF provides a buffered 2.35 V common-mode bias voltage used to set the DC level of differential analog inputs. It can drive transformer center taps or op-amp common-mode nodes and must be bypassed with ≥4.7 µF ceramic capacitance to GND for stability and low-noise performance - a requirement explicitly stated in the datasheet.

Does the LTC1746IFW#PBF support daisy-chained or interleaved sampling configurations?

No - the LTC1746IFW#PBF is a single-channel, non-interleaved ADC with fixed 25 Msps sampling and 5-cycle deterministic latency. It lacks synchronization inputs (e.g., SYSREF, SYNC) or multi-device timing controls required for interleaving. For higher effective sample rates, designers must use external clock dividers or parallel ADC architectures with dedicated alignment circuitry.