Analog Devices Inc. LTC1749IFW#TRPBF

Overview

LTC1749IFW#TRPBF from Analog Devices (formerly Linear Technology) is a 12-bit, 80Msps pipelined analog-to-digital converter with integrated PGA front end, 500MHz sample-and-hold bandwidth, ±1LSB INL, and 71.8dB SNR at 5MHz (PGA = 0). It operates from a single 5V supply and supports direct IF sampling in wideband receivers.

For engineers reviewing the LTC1749IFW#TRPBF datasheet, LTC1749IFW#TRPBF pinout, LTC1749IFW#TRPBF application, or LTC1749IFW#TRPBF equivalent, key selection criteria include input range configurability (±0.7V to ±1.125V differential), ultralow 0.15psRMS aperture jitter, dual reference selection, and flow-through 48-pin TSSOP layout compatibility with LTC1750.

Technical Context

The LTC1749IFW#TRPBF implements a four-stage CMOS pipelined ADC architecture with on-chip PGA and differential S/H circuitry. Its 500MHz full-power bandwidth enables undersampling of IF signals up to 350MHz while maintaining 80dB SFDR at 250MHz input.

It features differential ENC/ENC encode inputs compatible with PECL, GTL, TTL, or sinusoidal drive, plus separate OVDD (0.5V–5V) for interfacing directly to low-voltage DSPs or FIFOs. The VCM pin provides a stable 2.0V common-mode bias with ±30ppm/°C tempco.

Key Specifications

Pinout & Package

48-pin TSSOP package with flow-through pinout optimized for high-speed layout: analog and digital grounds separated, differential inputs and encode signals placed for matched trace routing, and dedicated VCM and SENSE pins for flexible reference configuration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with LTC1750CFW#PBF and AD9233BCPZ-80, the LTC1749IFW#TRPBF uniquely balances 12-bit fidelity, integrated PGA flexibility, and ultralow jitter in a proven TSSOP layout-making it optimal for cost-sensitive, high-dynamic-range IF sampling where board area and analog front-end simplicity are critical.

Availability

LTC1749IFW#TRPBF is available at Aetrix Electronics and suitable for cellular base station receivers, spectrum analyzers, communications test equipment, and direct IF sampling receivers requiring stable component supply across industrial temperature ranges (–40°C to +85°C).

Supply support for LTC1749IFW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its high-performance signal chain portfolio, emphasizing precision, speed, and reliability for demanding analog applications.

The LTC1749IFW#TRPBF belongs to Linear's high-speed ADC product line, designed specifically for wideband communications infrastructure where direct RF sampling, low jitter, and flexible input scaling are essential.

FAQ

What is the operating temperature range for the LTC1749IFW#TRPBF?

The LTC1749IFW#TRPBF is rated for industrial operation from –40°C to +85°C (I-grade), making it suitable for base station outdoor units and field-deployable test equipment. This is confirmed in the Absolute Maximum Ratings table where LTC1749I specifies the –40°C to 85°C range, and the part number suffix "IFW" explicitly denotes the I-grade TSSOP variant.

Does the LTC1749IFW#TRPBF require an external reference voltage?

No, the LTC1749IFW#TRPBF includes an internal 2V bandgap reference and supports two selectable full-scale ranges (0.7V or 1.125V) via the SENSE pin. External reference is optional and only needed if higher accuracy or custom scaling is required; the internal reference achieves ±20ppm/°C tempco with external 4.7µF bypassing.

How does the PGA function affect the input range of the LTC1749IFW#TRPBF?

The PGA in the LTC1749IFW#TRPBF provides two gain settings: PGA = LOW gives unity gain (1×), PGA = HIGH gives 1.67× gain. With internal VREF = 1.125V, this yields differential input ranges of ±1.125V (PGA = 0) or ±0.675V (PGA = 1). The SENSE pin further scales VREF, allowing fine-tuned range selection for varying signal amplitudes.

Can the LTC1749IFW#TRPBF interface directly with a 1.8V FPGA or DSP?

Yes, the LTC1749IFW#TRPBF supports OVDD from 0.5V to 5V, enabling direct connection to 1.8V logic without level shifters. Digital outputs D0–D11 and CLKOUT are driven from the OVDD rail, and VOH/VOL specifications (e.g., VOH = 1.74V min at OVDD = 1.8V, IO = –10µA) confirm compatibility with standard 1.8V CMOS interfaces.

What is the data latency of the LTC1749IFW#TRPBF, and how is it synchronized?

The LTC1749IFW#TRPBF has a fixed 5-cycle pipeline latency from ENC edge to valid data on D0–D11. This latency is deterministic and synchronized to CLKOUT, which rises 1–4ns after ENC (t4 parameter). The rising edge of CLKOUT serves as the data-valid strobe, ensuring reliable capture by downstream logic regardless of process/voltage/temperature variation.