Analog Devices Inc. LTC1922EN-1#PBF
- Part No.:
- LTC1922EN-1#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
LTC1922EN-1#PBF.pdf
- Description:
- IC REG CTRLR FULL-BRIDGE 20DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC1922EN-1#PBF from Analog Devices (formerly Linear Technology) is a synchronous phase-modulated full-bridge PWM controller designed for zero-voltage-switched (ZVS), isolated DC/DC converters. It delivers adaptive active/passive leg delay control, integrated synchronous rectifier drive for current-doubler topologies, and peak current mode control with programmable slope compensation. It targets high-efficiency, high-current 3.3V/5V outputs from 36–72V inputs in telecom and server power supplies.
For engineers reviewing the LTC1922EN-1#PBF datasheet, LTC1922EN-1#PBF pinout, LTC1922EN-1#PBF application, or LTC1922EN-1#PBF equivalent, key selection considerations include ZVS timing adaptivity across input voltage and load, secondary-side synchronous rectifier drive capability (OUTE/OUTF), fixed-frequency operation up to 1 MHz, 20-pin PDIP package compatibility, and integrated 5V/15mA LDO reference.
Technical Context
The LTC1922EN-1#PBF implements a phase-shifted full-bridge topology using DirectSense™ adaptive ZVS control: ADLY and PDLY pins monitor active/passive bridge leg voltages referenced to SBUS, enabling real-time turn-on timing independent of component tolerances. Its internal oscillator sets fixed frequency (236–319 kHz typ), while COMP pin interfaces with an error amplifier for voltage-mode feedback or current-mode loop stabilization.
It integrates six 50mA gate drivers (OUTA–OUTF) - OUTA/OUTB for passive-leg high/low side, OUTC/OUTD for active-leg high/low side, and OUTE/OUTF for secondary-side current-doubler synchronous rectifiers. The device features programmable leading-edge blanking (via RLEB), cycle-by-cycle current limiting (CS pin threshold 0.34–0.48 V), and hiccup-mode short-circuit protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology Support | Phase-shifted full-bridge with ZVS; supports current-doubler synchronous rectification on secondary side. |
| Oscillator Frequency | 236–319 kHz typical; fixed-frequency operation enables predictable EMI filtering and transformer design. |
| Driver Outputs | Six 50mA push-pull drivers: four primary-side (OUTA–OUTD), two secondary-side (OUTE/OUTF) for synchronous rectifiers. |
| Current Limit Threshold | 0.34–0.48 V on CS pin; enables precise cycle-by-cycle overcurrent protection without external scaling. |
| VCC Shunt Regulator | 10.2–10.8 V at 10 mA; provides self-biasing from high-voltage input rails with 4.2 V UVLO hysteresis. |
| Reference Output | 5.0 V ±1% (4.925–5.075 V), 15 mA capable; powers external circuitry and sets RLEB/RAMP bias points. |
| Start-Up Current | 145–250 µA typical; enables use of high-value (e.g., 100 kΩ) start-up resistors in offline applications. |
Pinout & Package
Package: 20-pin plastic DIP (PDIP), through-hole mounting, θJA = 62°C/W, rated for –40°C to 85°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OUTA, OUTB | Passive leg high/low side drivers | Drive MOSFETs in diagonal pair; OUTA high-side requires level-shifting; OUTB ground-referenced. |
| OUTC, OUTD | Active leg high/low side drivers | OUTC high-side driver enables ZVS via DirectSense; OUTD ground-referenced low-side switch. |
| OUTE, OUTF | Secondary-side synchronous rectifier drivers | Directly drive current-doubler SR MOSFETs on isolated output side; eliminate external logic or isolation. |
| ADLY, PDLY | ZVS delay sensing inputs | Monitor active/passive bridge leg voltages; threshold set by SBUS; enable adaptive turn-on timing. |
| SBUS | Bus voltage sense reference | Sets ADLY/PDLY thresholds proportional to VIN; enables ZVS optimization across 36–72 V input range. |
| CS | Current sense input | Accepts shunt or transformer-sense voltage; hosts slope compensation current for stable current-mode control. |
| COMP | Error amplifier output | Drives phase modulator; interfaces with optocoupler feedback loop or secondary-side controller. |
| VREF | 5 V reference output | Supplies 15 mA; used for RLEB, CT timing, and external bias; bypass with ≥1 µF ceramic capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive ZVS Delay Control | DirectSense™ circuitry dynamically adjusts turn-on timing for both active and passive legs using ADLY/PDLY/SBUS, eliminating manual trim and ensuring ZVS across full load and line range. |
| Integrated Secondary-Side Drive | OUTE and OUTF provide matched, timed 50mA gate drive signals for current-doubler synchronous rectifiers-no external isolation or timing logic required. |
| Programmable Leading Edge Blanking | RLEB pin accepts 10k–100k resistor to set blanking time (40–310 ns); prevents false triggering from switching noise on CS without external RC filters. |
| Low Start-Up & Quiescent Current | 145 µA typical start-up current and 4–7 mA operating current simplify auxiliary bias design and reduce no-load losses. |
| Comprehensive Protection Suite | Includes undervoltage lockout (10.25–10.7 V), hiccup-mode short-circuit response, soft-start (SS pin), and shutdown current limit (0.55–0.73 V on CS). |
Applications
| Telecom Rectifier Modules | Server VRM Power Stages |
|---|---|
|
Use Scenario: 48 V input telecom rectifier delivering 3.3 V/60 A to base station processors. IC Role / Device Role / Timing Role: LTC1922EN-1#PBF controls ZVS full-bridge primary and drives synchronous rectifiers on secondary; regulates output via isolated FB loop. Use Value: Achieves >90% efficiency at full load (VIN = 48 V) by eliminating body-diode conduction loss and enabling optimal duty cycle via adaptive delay. |
Use Scenario: High-density 12 V to 3.3 V intermediate bus converter in rack-mounted server PSU. IC Role / Device Role / Timing Role: LTC1922EN-1#PBF implements phase-shifted full-bridge with current-doubler output; manages transformer flux balance and ZVS transitions. Use Value: Enables compact magnetics and reduced thermal stress via fixed-frequency ZVS, supporting >500 W/in³ power density. |
| Distributed Power Architectures | Industrial Isolated DC/DC Converters |
|
Use Scenario: 36–72 V input, 5 V/30 A isolated module powering FPGA I/O banks in industrial PLCs. IC Role / Device Role / Timing Role: LTC1922EN-1#PBF serves as primary-side controller with adaptive ZVS and secondary-side synchronous rectifier timing. Use Value: Maintains >85% efficiency down to 10% load via low quiescent current (4–7 mA) and optimized light-load timing. |
Use Scenario: Wide-input (36–72 V) isolated 12 V/10 A supply for motor control gate drivers in factory automation. IC Role / Device Role / Timing Role: LTC1922EN-1#PBF executes phase-shifted control with programmable slope compensation for stability under variable load transients. Use Value: Ensures robust current-mode loop stability across temperature (–40°C to 85°C) and input variation without external compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar full-bridge ZVS controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC3895N | Fixed-delay ZVS control; no adaptive DirectSense™; requires external slope compensation; 16-pin SOIC. | Lacks integrated secondary-side synchronous rectifier drive; needs external logic for current-doubler timing. | Choose UCC3895N only if legacy design reuse or cost sensitivity outweighs need for adaptive ZVS and simplified layout. |
| LTC3722-1IGN#PBF | Successor IC with enhanced ZVS algorithm, higher frequency (up to 1 MHz), and improved current-sense accuracy; 24-pin SSOP. | Requires PCB redesign due to different pinout and package; supports wider VIN range (4.5–60 V) but lower max output current capability. | Select LTC3722-1IGN#PBF for new designs requiring higher switching frequency or tighter current-limit tolerance; not drop-in compatible. |
Compared with UCC3895N, LTC1922EN-1#PBF delivers superior ZVS adaptivity and eliminates external SR timing logic; versus LTC3722-1IGN#PBF, it offers proven reliability in mature telecom systems and direct PDIP compatibility for through-hole manufacturing.
Availability
LTC1922EN-1#PBF is available at Aetrix Electronics and suitable for telecom rectifier modules, server VRM power stages, and industrial isolated DC/DC converters requiring stable component supply, long-term lifecycle support, and through-hole assembly compatibility.
Supply support for LTC1922EN-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving precision instrumentation, communications, and power conversion markets.
The LTC1922EN-1#PBF belongs to Linear's legacy high-efficiency power controller family, engineered specifically for zero-voltage-switched full-bridge topologies in telecom and server infrastructure where efficiency, reliability, and adaptive timing are critical.
FAQ
What is the operating temperature range for the LTC1922EN-1#PBF?
The LTC1922EN-1#PBF is specified for operation from –40°C to +85°C ambient temperature. This rating applies to the N-package (20-pin PDIP) variant and is guaranteed per the datasheet's electrical characteristics table. Thermal derating is not required within this range when mounted per JEDEC standards with θJA = 62°C/W.
Does the LTC1922EN-1#PBF support both voltage-mode and current-mode control?
Yes, the LTC1922EN-1#PBF supports both control modes. Voltage-mode operation uses the FB pin for optocoupler feedback into the error amplifier. Current-mode operation uses the CS pin for primary-side current sensing with programmable slope compensation (via ISLP current sourced into CS), enabling stable loop response across wide load and line variations.
How does the DirectSense™ ZVS control work on the LTC1922EN-1#PBF?
The LTC1922EN-1#PBF implements DirectSense™ ZVS by monitoring ADLY and PDLY pins - which connect to voltage dividers on the active and passive bridge legs - referenced to SBUS. When the sensed voltage crosses the SBUS-derived threshold, the controller triggers MOSFET turn-on precisely at zero voltage crossing, adapting in real time to input voltage, load, and component tolerances without external trim.
Can the LTC1922EN-1#PBF drive synchronous rectifiers on the secondary side without external components?
Yes. The LTC1922EN-1#PBF provides dedicated 50mA gate drivers on OUTE and OUTF pins specifically for secondary-side current-doubler synchronous rectifiers. These outputs are internally timed and isolated from primary-side switching noise, eliminating the need for external timing logic, isolation transformers, or discrete drivers in compliant designs.
What is the purpose of the RLEB pin on the LTC1922EN-1#PBF?
The RLEB pin on the LTC1922EN-1#PBF sets leading-edge blanking time (40–310 ns) via an external resistor (10k–100k Ω). This blanks the CS comparator during MOSFET turn-on to suppress false overcurrent trips caused by transformer leakage inductance spikes - a critical feature for stable current-mode operation in full-bridge topologies.
LTC1922EN-1#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Positive, Isolation Capable
- Topology:
- Full-Bridge
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 3.8V ~ 10.3V
- Frequency - Switching:
- Up to 1MHz
- Duty Cycle (Max):
- 99%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Ramp, Soft Start
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 20-PDIP
LTC1922EN-1#PBF FAQ
1.How can I place an order for LTC1922EN-1#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC1922EN-1#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC1922EN-1#PBF reliable?
The price and inventory of LTC1922EN-1#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC1922EN-1#PBF is usually 5 days.
3.What payment methods are accepted for LTC1922EN-1#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC1922EN-1#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC1922EN-1#PBF?
LTC1922EN-1#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC1922EN-1#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC1922EN-1#PBF?
For technical support, including LTC1922EN-1#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC1922EN-1#PBF requirements.
6.How does Aetrix verify that LTC1922EN-1#PBF is sourced from the original manufacturer or authorized distributors?
All LTC1922EN-1#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC1922EN-1#PBF meets industry standards.
7.What is the process for return or replacement of LTC1922EN-1#PBF?
All LTC1922EN-1#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC1922EN-1#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC1922EN-1#PBF part is unused and in its original packaging.
Return procedure for LTC1922EN-1#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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