Analog Devices Inc. LTC2122CUK#PBF

Overview

LTC2122CUK#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, 14-bit, 170Msps analog-to-digital converter with JESD204B serial output interface. It performs simultaneous sampling of high-frequency wide-dynamic-range signals in communications infrastructure, featuring 70dBFS SNR, 90dBFS SFDR, and 1.25GHz full-power input bandwidth. It operates from a single 1.8V analog supply and supports both one-lane (6.0Gbps) and two-lane (2 × 3.4Gbps) JESD204B configurations.

For engineers reviewing the LTC2122CUK#PBF datasheet, LTC2122CUK#PBF pinout, LTC2122CUK#PBF application, or LTC2122CUK#PBF equivalent, key selection criteria include deterministic latency support (Subclass 1/2), CML output drive capability (10–16mA), clock divide-by-two option, SPI configuration interface, and 48-lead 7mm × 7mm QFN thermal performance (θ_JA = 28°C/W).

Technical Context

The LTC2122CUK#PBF integrates two independent 14-bit ADC cores sharing a common DEVCLK input, with internal PLL and programmable clock dividers enabling deterministic latency alignment via SYSREF or SYNC~ signals. Its JESD204B serializer supports 8B/10B encoding, lane alignment sequence (LAS), and comma detection for FPGA/ASIC synchronization.

It features dual CML output lanes (CMLOUT_A0±, CMLOUT_B0±) configurable for either per-channel 3.4Gbps transmission or shared 6.0Gbps single-lane operation. Input sampling is synchronized to DEVCLK edges-falling edge in 1× mode, rising edge in 2× mode-with aperture jitter specified at 0.15ps_RMS and acquisition delay at 1ns.

Key Specifications

Pinout & Package

Package: 48-lead (7mm × 7mm) plastic QFN with exposed thermal pad (Pin 49 = GND). Requires soldering of exposed pad to PCB ground plane for thermal management (θ_JA = 28°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.

Compared with AD9680BCPZ-500 and LTC2262IUK#PBF, the LTC2122CUK#PBF delivers optimal balance of 170Msps performance, JESD204B lane efficiency, and 751mW power in a thermally robust 7mm QFN - making it ideal for space-constrained, multi-converter communications systems requiring precise timing alignment.

Availability

LTC2122CUK#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and high-definition medical imaging requiring stable component supply across extended production lifecycles.

Supply support for LTC2122CUK#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, automotive, and healthcare markets.

The LTC2122CUK#PBF belongs to ADI's high-speed data converter product line, designed specifically for demanding communications infrastructure applications requiring wide input bandwidth, low jitter, and JESD204B deterministic latency support.

FAQ

What is the maximum sampling rate supported by the LTC2122CUK#PBF?

The LTC2122CUK#PBF supports a maximum sampling rate of 170Msps across both channels simultaneously. This rate is achievable with either single-lane (6.0Gbps) or dual-lane (2 × 3.4Gbps) JESD204B operation. At 170Msps, the device maintains 70dBFS SNR and 90dBFS SFDR for 70MHz input signals, as verified in the official datasheet under typical performance conditions (VDD = 1.8V, f_IN = 70MHz, –1dBFS).

Does the LTC2122CUK#PBF support deterministic latency, and how is it configured?

Yes, the LTC2122CUK#PBF supports deterministic latency via JESD204B Subclass 1 or Subclass 2 operation. In Subclass 1, a rising edge on SYSREF+ / SYSREF– (Pins 18/19) resets internal dividers and aligns latency across devices. In Subclass 2, SYNC~+ / SYNC~– (Pins 21/22) serves this function. The LTC2122CUK#PBF implements both modes with documented latencies: LATP1 = 10.5t_S (single-lane), LATP2 = 13.5t_S (dual-lane), and deterministic LAS/overflow delays per datasheet Table 1.

What are the power supply requirements for the LTC2122CUK#PBF?

The LTC2122CUK#PBF requires two dedicated supplies: VDD (1.7V to 1.9V, typ. 1.8V) for analog and digital core logic, and OVDD (1.2V to 1.9V) for CML output drivers. Total power dissipation is 751mW at 170Msps with VDD = 1.8V (excluding OVDD power). Sleep mode reduces consumption to 2mW. All VDD pins must be bypassed with 0.1µF ceramic capacitors to GND, and OVDD pairs require individual 0.1µF decoupling per datasheet Pin Functions section.

Can the LTC2122CUK#PBF operate with an external reference, and what is the input range impact?

Yes, the LTC2122CUK#PBF supports external reference via the SENSE pin (Pin 5). Applying 1.2V to 1.3V to SENSE selects an input range of ±0.6 × V_SENSE, e.g., ±0.72V for 1.2V reference. With internal reference (SENSE tied to VDD), the input range is ±0.75V. The device specifies V_SENSE tolerance of ±1.25%, and leakage current is ±1µA over temperature - ensuring stable scaling without additional buffering circuitry.

What package type and thermal characteristics does the LTC2122CUK#PBF use?

The LTC2122CUK#PBF uses a 48-lead plastic QFN package measuring 7mm × 7mm with an exposed thermal pad (Pin 49 = GND). Its thermal resistance is θ_JA = 28°C/W when the exposed pad is soldered to a minimum 1in² copper area on the PCB. This package enables efficient heat dissipation in high-density RF modules and complies with JEDEC standards for lead-free (Pb-free) finish, as indicated by the "#PBF" suffix in the part number.