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Analog Devices Inc. LTC2122CUK#TRPBF
- Part No.:
- LTC2122CUK#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LTC2122CUK#TRPBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 48QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,260
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Product details
Overview
LTC2122CUK#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel, simultaneous-sampling 14-bit analog-to-digital converter with JESD204B serial interface, operating at up to 170Msps. It delivers 70dBFS SNR and 90dBFS SFDR at 70MHz input, features 1.25GHz full-power bandwidth, and uses a single 1.8V analog supply. It is deployed in high-performance communications signal digitization, including cellular base station receivers and software-defined radios.
For engineers reviewing the LTC2122CUK#TRPBF datasheet, LTC2122CUK#TRPBF pinout, LTC2122CUK#TRPBF application, or LTC2122CUK#TRPBF equivalent, key selection criteria include JESD204B lane configuration (1-lane shared vs. 2-lane independent), deterministic latency support via SYSREF/SYNC~, clock divide-by-two capability, CML output drive current programmability (10–16mA), and internal/external reference selection via SENSE pin.
Technical Context
The LTC2122CUK#TRPBF integrates two independent 14-bit ADC cores sharing a common DEVCLK input, with configurable clock division (1× or 2×) and optional duty cycle stabilization. Its JESD204B serializer supports Subclass 0, 1, and 2 operation, enabling deterministic latency alignment using SYSREF (Subclass 1) or SYNC~ (Subclass 2).
Each channel features a dedicated CML output pair (CMLOUT_A0±, CMLOUT_B0±) supporting either 3.4Gbps per lane (two-lane mode) or 6.0Gbps on a single lane (one-lane mode). The analog front end includes programmable input range (±0.75V internal or ±0.6×VSENSE external), VCM bias generation, and 75dB common-mode rejection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes - guarantees monotonic transfer function for precision measurement applications. |
| Sampling Rate | Up to 170Msps - enables Nyquist sampling of signals up to 85MHz or undersampling of RF carriers up to 1.25GHz. |
| SNR @ 70MHz | 70dBFS - provides ≥11.6 effective bits for high-fidelity signal capture in wideband receivers. |
| SFDR @ 70MHz | 90dBFS - suppresses spurious tones below –90dB relative to full-scale, critical for multi-carrier cellular systems. |
| Input Bandwidth | 1.25GHz full-power - supports direct RF sampling of L-band and S-band frequencies without external IF filtering. |
| Power Dissipation | 751mW total at 170Msps - balances performance and thermal management in dense FPGA-ADC subsystems. |
| JESD204B Lanes | Configurable 1-lane (6.0Gbps) or 2-lane (2 × 3.4Gbps) - reduces PCB routing complexity and FPGA I/O count. |
Pinout & Package
48-lead (7mm × 7mm) plastic QFN package with exposed thermal pad (Pin 49 = GND, must be soldered to PCB). Pin functions validated per Linear Technology LTC2122 datasheet Rev. FB.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pins 1,12,13,23,24,37,38,48) | Analog power supply | 1.8V ±0.1V supply; requires local 0.1µF ceramic bypassing; multiple pins reduce IR drop and noise coupling. |
| AINA+/AINA– (Pins 3,4) | Differential analog input Channel A | Accepts 1.5VP-P differential signal; common-mode set by VCM; supports DC-coupled or AC-coupled interfaces. |
| DEVCLK+/DEVCLK– (Pins 15,16) | Differential sampling clock input | Accepts LVDS/PECL/sine wave; internal divider supports 1× or 2× clock-to-sample ratio; determines sampling edge timing. |
| SYSREF+/SYSREF– (Pins 18,19) | JESD204B Subclass 1 synchronization | Edge-triggered reset for deterministic latency; required for time-aligned multi-device systems (e.g., MIMO antenna arrays). |
| CMLOUT_A0+/CMLOUT_A0– (Pins 31,32) | JESD204B CML serial output | Programmable 10–16mA drive; supports 50Ω to OVDD or 100Ω differential termination; 3.4Gbps (2-lane) or 6.0Gbps (1-lane) operation. |
| SYNC~+/SYNC~– (Pins 21,22) | JESD204B subclass synchronization | Triggers K28.5 comma insertion and lane alignment; used for initial code-group sync in all subclasses; enables Subclass 2 deterministic latency. |
| SENSE (Pin 5) | Reference selection control | Connect to VDD for internal 1.25V reference and ±0.75V input range; apply 1.2–1.3V external reference for ±0.6×VSENSE range. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel simultaneous sampling | Enables coherent I/Q demodulation and phase-matched signal acquisition without inter-channel skew. |
| JESD204B Subclass 1 & 2 support | Allows deterministic latency alignment across multiple converters-essential for beamforming and phased-array radar. |
| Programmable CML output current (10–16mA) | Permits optimization of signal integrity vs. power: lower current for short traces, higher current for longer FR4 runs. |
| Internal clock divide-by-two with duty cycle stabilizer | Relaxes clock source requirements: accepts asymmetric clocks while maintaining aperture jitter <0.15ps RMS. |
| Low-power Nap mode (433mW) | Reduces power by >40% during idle periods while retaining register state and enabling fast wake-up (<1µs). |
Applications
| Cellular Base Station Receiver | Software Defined Radio (SDR) |
|---|---|
|
Use Scenario: Digitizing 20–100MHz instantaneous bandwidth from multi-antenna LTE/NR RF front ends. IC Role / Device Role / Timing Role: Dual-channel ADC captures synchronized I/Q data streams; JESD204B transfers samples directly to FPGA-based digital downconverters. Use Value: 90dBFS SFDR prevents adjacent-channel interference masking weak signals; 1.25GHz bandwidth enables direct sampling of 3.5GHz NR bands. |
Use Scenario: Reconfigurable wideband receiver supporting multiple waveforms (FM, DVB-T, LTE) across 100kHz–2GHz. IC Role / Device Role / Timing Role: High-dynamic-range ADC front end feeding FPGA-based modulation/demodulation engines; SYSREF enables waveform-switching latency consistency. Use Value: 70dBFS SNR ensures clean baseband reconstruction; SPI-configurable clock division simplifies clock tree design across frequency bands. |
| Medical Ultrasound Beamformer | Test & Measurement Digitizer |
|
Use Scenario: Capturing echo return signals from 2–15MHz transducer arrays with precise time-of-flight resolution. IC Role / Device Role / Timing Role: Simultaneous sampling across 64+ channels (using multiple LTC2122 devices); SYNC~ aligns frame boundaries across all converters. Use Value: –90dB crosstalk prevents channel bleed in beam synthesis; low 0.15ps RMS aperture jitter enables sub-millimeter spatial resolution. |
Use Scenario: High-speed oscilloscope or spectrum analyzer front end requiring >100MHz real-time bandwidth and low harmonic distortion. IC Role / Device Role / Timing Role: Primary digitizer stage feeding real-time FFT and envelope detection logic; CML outputs drive FPGA transceivers with minimal equalization. Use Value: 6.0Gbps single-lane mode reduces FPGA pin count and layout complexity; 75dB CMRR rejects common-mode noise from probe grounds. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9680BCPZ-500 | 14-bit, 500Msps dual ADC; JESD204B Subclass 1 only; 1.35GHz BW; 1.25V supply; higher power (1.6W). | Targeted at wider instantaneous bandwidth (>250MHz) and higher sample rates; requires more aggressive thermal design. | Select when >250MHz real-time bandwidth is required and FPGA has sufficient JESD204B lanes for 500Msps throughput. |
| ADS54J60IRGCT | 16-bit, 500Msps dual ADC; JESD204B Subclass 2; 900MHz BW; 1.9V/1.2V dual supply; 1.8W power. | Higher resolution for dynamic range-critical applications (e.g., radar pulse compression); lacks clock duty cycle stabilizer. | Select when 16-bit ENOB is mandatory and deterministic latency via SYNC~ suffices; avoid if clock source has poor duty cycle. |
Compared with AD9680BCPZ-500 and ADS54J60IRGCT, the LTC2122CUK#TRPBF offers optimal balance of 170Msps performance, 751mW power, integrated clock conditioning, and flexible JESD204B subclass support-making it ideal for cost- and power-sensitive 100–200MHz bandwidth systems where 14-bit resolution is sufficient.
Availability
LTC2122CUK#TRPBF is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio, and medical ultrasound applications requiring stable component supply, long-term production continuity, and RoHS-compliant packaging.
Supply support for LTC2122CUK#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2122CUK#TRPBF belongs to ADI's high-speed data converter product line, designed specifically for demanding communications and instrumentation applications requiring high dynamic range, low jitter, and JESD204B interoperability with FPGAs and ASICs.
FAQ
What is the maximum sampling rate supported by the LTC2122CUK#TRPBF?
The LTC2122CUK#TRPBF supports a maximum sampling rate of 170Msps per channel. At this rate, it achieves 70dBFS SNR and 90dBFS SFDR at 70MHz input frequency. Operation above 150Msps requires two independent JESD204B lanes (3.4Gbps each); below 150Msps, both channels can share one lane at 6.0Gbps. The device's 1.25GHz full-power bandwidth enables undersampling of RF signals far beyond its Nyquist frequency.
Does the LTC2122CUK#TRPBF support deterministic latency, and how is it configured?
Yes, the LTC2122CUK#TRPBF supports deterministic latency in JESD204B Subclass 1 and Subclass 2 modes. In Subclass 1, a rising edge on SYSREF+ / SYSREF– (Pins 18/19) resets internal dividers and establishes fixed latency. In Subclass 2, a rising edge on SYNC~+ / SYNC~– (Pins 21/22) performs the same function. Latency values are documented: 10.5tS (single-lane) and 13.5tS (dual-lane), where tS is the sampling period. This enables precise time alignment across multiple LTC2122CUK#TRPBF devices in phased-array systems.
How does the SENSE pin affect the LTC2122CUK#TRPBF's input range and reference configuration?
The SENSE pin (Pin 5) selects between internal and external reference modes. When tied to VDD, the LTC2122CUK#TRPBF uses its internal 1.25V reference and provides a ±0.75V differential input range (1.5VP-P). When an external voltage of 1.2–1.3V is applied to SENSE, the device uses that voltage as reference and scales the input range to ±0.6 × VSENSE. This allows matching to external DACs or custom front-end gain stages while maintaining optimal SNR performance.
What are the power supply requirements for the LTC2122CUK#TRPBF's analog and output sections?
The LTC2122CUK#TRPBF requires two separate supplies: VDD (Pins 1,12,13,23,24,37,38,48) at 1.7–1.9V for analog circuitry, and OVDD (Pins 25,26,35,36) at 1.2–1.9V for CML output drivers. Total power dissipation is 751mW at 170Msps with VDD = 1.8V. The device also supports low-power Nap mode (433mW) and Sleep mode (2mW), both accessible via SPI register control without losing configuration state.
Can the LTC2122CUK#TRPBF operate with a single-ended clock input?
No, the LTC2122CUK#TRPBF requires a differential clock input on DEVCLK+ / DEVCLK– (Pins 15/16). It accepts LVDS, PECL, or sine wave inputs with ≥0.2V differential amplitude and common-mode voltage between 1.1V and 1.5V. Single-ended clock sources must be converted to differential using a transformer or dedicated buffer (e.g., ADCLK948) to meet input specifications and maintain <0.15ps RMS aperture jitter performance.
LTC2122CUK#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 170M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- JESD204B
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 48-QFN (7x7)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2122CUK#TRPBF FAQ
1.How can I place an order for LTC2122CUK#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2122CUK#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2122CUK#TRPBF reliable?
The price and inventory of LTC2122CUK#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2122CUK#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2122CUK#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2122CUK#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2122CUK#TRPBF?
LTC2122CUK#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2122CUK#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2122CUK#TRPBF?
For technical support, including LTC2122CUK#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2122CUK#TRPBF requirements.
6.How does Aetrix verify that LTC2122CUK#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2122CUK#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2122CUK#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2122CUK#TRPBF?
All LTC2122CUK#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2122CUK#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2122CUK#TRPBF part is unused and in its original packaging.
Return procedure for LTC2122CUK#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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