Analog Devices Inc. LTC2122IUK#PBF

Overview

LTC2122IUK#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, simultaneous-sampling 14-bit analog-to-digital converter with JESD204B serial interface, operating at up to 170Msps. It delivers 70dBFS SNR and 90dBFS SFDR at 70MHz input, features 1.25GHz full-power bandwidth, and supports single 1.8V analog supply. It is deployed in cellular base station receivers for high-fidelity RF digitization.

For engineers reviewing the LTC2122IUK#PBF datasheet, LTC2122IUK#PBF pinout, LTC2122IUK#PBF application, or LTC2122IUK#PBF equivalent, key selection criteria include JESD204B lane count configuration (1-lane shared vs. 2-lane independent), deterministic latency support across Subclass 1/2, CML output drive current programmability (10–16mA), and internal/external reference selection via SENSE pin.

Technical Context

The LTC2122IUK#PBF integrates two independent 14-bit ADC cores sharing a common DEVCLK input, with optional divide-by-two clock circuitry and duty cycle stabilizer to maintain sampling accuracy across wide clock duty cycles. Its JESD204B serializer supports both Subclass 1 (SYSREF-triggered initialization) and Subclass 2 (SYNC~-triggered initialization) for deterministic latency alignment.

Each channel features fully differential analog inputs (AINA±, AINB±), programmable input range (±0.75V internal or ±0.6×V_SENSE external), and separate CML output pairs (CMLOUT_A0±, CMLOUT_B0±) configurable for 3.4Gbps (2-lane) or 6.0Gbps (1-lane) operation. The SPI interface enables real-time register control of clock dividers, power modes, and output drivers.

Key Specifications

Pinout & Package

Package: 48-lead (7mm × 7mm) plastic QFN with exposed thermal pad (Pin 49 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel 14-bit ADC applications.

Compared with AD9680BCPZ-500 and ADS54J60IRGC, the LTC2122IUK#PBF provides balanced performance at 170Msps with integrated clock division, dual-subclass JESD204B flexibility, and lower power-making it optimal for thermally constrained, mid-band wireless infrastructure where deterministic latency and ease of clock management are prioritized over raw speed.

Availability

LTC2122IUK#PBF is available at Aetrix Electronics and suitable for cellular base stations, software defined radios, and medical ultrasound imaging requiring stable component supply across industrial temperature ranges (–40°C to +85°C).

Supply support for LTC2122IUK#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017, inheriting its high-performance signal chain portfolio including precision ADCs, DACs, and RF components.

The LTC2122IUK#PBF belongs to Linear's ultra-high-speed ADC family designed specifically for communications infrastructure demanding wide bandwidth, low jitter, and JESD204B interoperability with FPGAs and ASICs.

FAQ

What is the operating temperature range for the LTC2122IUK#PBF?

The LTC2122IUK#PBF is rated for –40°C to +85°C ambient operation, matching the "I" grade designation in its part number. This extended industrial temperature range ensures reliable performance in outdoor cellular base station enclosures and mobile medical equipment where thermal cycling occurs. All specified AC and DC parameters-including SNR, SFDR, and integral linearity-are guaranteed across this full range.

Does the LTC2122IUK#PBF support both JESD204B Subclass 1 and Subclass 2?

Yes, the LTC2122IUK#PBF supports both JESD204B Subclass 1 and Subclass 2. Subclass 1 uses SYSREF+ and SYSREF– pins for deterministic latency initialization, while Subclass 2 uses SYNC~+ and SYNC~– pins. The LTC2122IUK#PBF's internal logic detects the active subclass at power-up based on register configuration and synchronizes accordingly-enabling flexible integration into diverse FPGA-based systems.

How is the input range configured on the LTC2122IUK#PBF?

The LTC2122IUK#PBF input range is configured via the SENSE pin (Pin 5). Connecting SENSE to VDD selects the internal 1.25V reference and a ±0.75V differential input range. Applying an external 1.2V–1.3V reference to SENSE selects a ±0.6×V_SENSE range-for example, 1.25V yields ±0.75V, matching the internal option. This dual-mode flexibility simplifies front-end amplifier gain design across different signal chain architectures.

What are the power supply requirements for the LTC2122IUK#PBF?

The LTC2122IUK#PBF requires two independent supplies: VDD (1.7V–1.9V, typical 1.8V) for analog and digital core circuits, and OVDD (1.2V–1.9V) for CML output drivers. VDD pins (eight total) must be bypassed with 0.1µF ceramic capacitors near each group; OVDD pairs require individual 0.1µF bypassing. Separating OVDD allows noise isolation between analog conversion and high-speed serial output domains.

Can the LTC2122IUK#PBF operate with a single JESD204B lane for both channels?

Yes, the LTC2122IUK#PBF supports single-lane operation at up to 6.0Gbps, multiplexing both ADC outputs onto one CML pair (CMLOUT_A0±). This mode is enabled via SPI register configuration and is valid for sample rates ≤150Msps. At 170Msps, two lanes (CMLOUT_A0± and CMLOUT_B0±) operating at 3.4Gbps each are required to meet JESD204B lane rate limits and maintain bit error rate integrity.