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Analog Devices Inc. LTC2122IUK#TRPBF
- Part No.:
- LTC2122IUK#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LTC2122IUK#TRPBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 48QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,728
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Product details
Overview
LTC2122IUK#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel, simultaneous-sampling 14-bit analog-to-digital converter with JESD204B serial interface, operating at up to 170Msps. It delivers 70dBFS SNR and 90dBFS SFDR at 70MHz input, features 1.25GHz full-power bandwidth, and uses a single 1.8V analog supply. It is deployed in high-performance communications signal digitization, including cellular base station receive chains.
For engineers reviewing the LTC2122IUK#TRPBF datasheet, LTC2122IUK#TRPBF pinout, LTC2122IUK#TRPBF application, or LTC2122IUK#TRPBF equivalent, key selection criteria include deterministic JESD204B latency (subclass 1/2 support), dual-ADC synchronization via SYSREF/SYNC~, CML output compliance at 3.4Gbps or 6.0Gbps, and low-power sleep/nap modes for power-constrained systems.
Technical Context
The LTC2122IUK#TRPBF integrates two independent 14-bit ADC cores sharing a common DEVCLK input, with optional divide-by-two clock circuitry and duty cycle stabilizer. Its JESD204B serializer supports both one-lane (6.0Gbps, dual-ADC multiplexed) and two-lane (3.4Gbps per lane) configurations, using 8B/10B encoding and CML physical layer drivers.
It employs internal reference (1.25V VREF, 0.435×VDD VCM) or external reference via SENSE pin, enabling ±0.75V or ±0.6×VSENSE input ranges. Analog inputs are fully differential with 1.5VP-P range, 75dB CMRR, and acquisition jitter of 0.15psRMS - critical for undersampling RF signals up to 383MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes - guarantees monotonic transfer function for precision measurement applications. |
| Sampling Rate | Up to 170Msps - supports wideband IF sampling in 5G NR and LTE-A receivers. |
| SNR @ 70MHz | 70dBFS - enables high-fidelity digitization of 16-QAM/64-QAM waveforms without quantization-limited EVM degradation. |
| SFDR @ 70MHz | 90dBFS - suppresses spurious tones below –90dB relative to full scale, essential for adjacent channel leakage ratio (ACLR) compliance. |
| Input Bandwidth | 1.25GHz full-power - allows direct RF sampling of L-band and S-band signals without external anti-alias filtering. |
| Power Dissipation | 751mW total at 170Msps - balances performance and thermal management in dense FPGA-ADC subsystems. |
| JESD204B Lanes | Configurable 1-lane (6.0Gbps) or 2-lane (3.4Gbps each) - reduces FPGA I/O count and PCB routing complexity versus parallel LVDS interfaces. |
Pinout & Package
48-lead (7mm × 7mm) plastic QFN package with exposed thermal pad (Pin 49 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pins 1,12,13,23,24,37,38,48) | Analog supply input | 1.8V ±0.1V supply; multiple pins reduce IR drop and enable localized 0.1µF ceramic bypassing. |
| AINA+/AINA– (Pins 3,4) | Differential analog input A | 1.5VP-P full-scale range; requires matched 50Ω termination and common-mode bias via VCM. |
| DEVCLK+/DEVCLK– (Pins 15,16) | Differential sampling clock input | Accepts sine/LVDS/PECL; supports 1× or 2× clock division to align sampling edge with system timing requirements. |
| SYSREF+/SYSREF– (Pins 18,19) | JESD204B subclass 1 synchronization | Resets internal dividers and establishes deterministic latency; sampled on rising DEVCLK edge. |
| SYNC~+/SYNC~– (Pins 21,22) | JESD204B frame alignment & subclass 2 sync | Triggers K28.5 comma transmission and resets latency counters in subclass 2 operation. |
| CMLOUT_A0+/CMLOUT_A0– (Pins 31,32) | JESD204B CML data output (lane 0) | Programmable 10–16mA drive; supports 50Ω-to-OVDD or 100Ω differential termination for 3.4/6.0Gbps operation. |
| CMLOUT_B0+/CMLOUT_B0– (Pins 29,30) | JESD204B CML data output (lane 1) | Active only in two-lane mode; identical electrical specs to lane 0 for balanced layout design. |
| CS/SDI/SCK/SDO (Pins 46,44,45,43) | 4-wire SPI configuration interface | 1.8–3.3V logic compatible; SDO is open-drain requiring external pull-up for readback capability. |
Key Features
| Feature | Design Value |
|---|---|
| Deterministic JESD204B latency | 10.5 tS (single-lane) or 13.5 tS (dual-lane) pipeline latency - enables precise time-of-arrival alignment across multi-ADC arrays in phased-array radar. |
| Optional clock divide-by-two | Enables use of lower-frequency, lower-jitter clocks while maintaining 170Msps sampling - simplifies clock tree design and improves SNR stability. |
| Low-power sleep/nap modes | 2mW sleep and 433mW nap power states - allows dynamic power scaling during idle periods in battery-backed or thermally constrained instrumentation. |
| 1.25GHz analog input bandwidth | Supports undersampling of RF carriers up to 383MHz at 170Msps - eliminates need for image-reject mixers in direct-conversion receivers. |
| Integrated reference & bias generation | VREF (1.25V ±25mV) and VCM (0.435×VDD ±18mV) outputs eliminate external reference ICs and reduce BOM count in compact designs. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
Use Scenario: Digitizing dual-channel IF signals in massive MIMO remote radio heads with 100MHz+ instantaneous bandwidth. IC Role / Device Role / Timing Role: Dual simultaneous-sampling ADC providing synchronized I/Q data streams to FPGA-based digital downconverters with deterministic JESD204B latency. Use Value: 90dBFS SFDR ensures ACLR compliance for 5G NR 100MHz channels; 1.25GHz BW enables direct sampling of 3.5GHz band signals at 2×IF. |
Use Scenario: Reconfigurable wideband receiver front-end supporting multiple waveforms (LTE, WiMAX, GPS) in military comms radios. IC Role / Device Role / Timing Role: High-dynamic-range ADC core enabling real-time spectrum analysis and adaptive filtering via FPGA fabric. Use Value: 70dBFS SNR preserves EVM under high-order modulation; JESD204B subclass 2 sync allows seamless waveform switching without resynchronization delay. |
| Medical Ultrasound Imaging | Test & Measurement Instrumentation |
Use Scenario: Beamforming digitization in portable ultrasound systems requiring high SNR and low power consumption. IC Role / Device Role / Timing Role: Dual-channel ADC capturing echo return signals from phased transducer arrays with precise inter-channel timing alignment. Use Value: 0.15psRMS aperture jitter minimizes time-of-flight measurement error; nap mode reduces average power during non-imaging intervals. |
Use Scenario: High-speed oscilloscope or vector signal analyzer front-end digitizing signals up to 140MHz with minimal distortion. IC Role / Device Role / Timing Role: Precision ADC delivering calibrated amplitude and phase data to DSP engines for spectral analysis and demodulation. Use Value: 75dB CMRR rejects common-mode noise from probe grounds; 14-bit resolution supports >80dB dynamic range measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, JESD204B ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9680BCPZ-500 | 14-bit, 500Msps, 2-lane JESD204B (12.5Gbps/lane); higher speed but 1.25W power; 72dBFS SNR @ 70MHz. | Targeted at higher-bandwidth radar and wideband spectrum monitoring where >170Msps is required. | Select AD9680BCPZ-500 when sample rate >250Msps is needed; LTC2122IUK#TRPBF remains optimal for cost- and power-sensitive 170Msps systems. |
| ADS54J60IRGCT | 14-bit, 500Msps, JESD204B subclass 1; 73dBFS SNR @ 70MHz; 1.8V/3.3V dual-supply; no integrated VCM/VREF. | Requires external reference/bias circuitry; suited for TI ecosystem designs with C66x DSPs or Sitara AM57x processors. | Choose ADS54J60IRGCT if leveraging TI's JESD204B PHY IP and existing 3.3V infrastructure; LTC2122IUK#TRPBF offers simpler single-supply integration. |
Compared with AD9680BCPZ-500 and ADS54J60IRGCT, the LTC2122IUK#TRPBF provides superior power efficiency (751mW vs >1.2W) and integrated analog support (VCM/VREF), making it ideal for thermally constrained, space-limited 170Msps applications where full 500Msps capability is unnecessary.
Availability
LTC2122IUK#TRPBF is available at Aetrix Electronics and suitable for cellular base stations, software defined radios, and medical ultrasound imaging requiring stable component supply across industrial temperature ranges (–40°C to +85°C).
Supply support for LTC2122IUK#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2122IUK#TRPBF belongs to ADI's high-speed data converter product line, designed specifically for demanding communications infrastructure applications requiring high dynamic range, deterministic latency, and JESD204B interoperability with FPGAs and ASICs.
FAQ
What is the operating temperature range for the LTC2122IUK#TRPBF?
The LTC2122IUK#TRPBF is rated for industrial temperature operation from –40°C to +85°C, as indicated by the "I" grade in its part number. This makes it suitable for deployment in outdoor base stations, ruggedized test equipment, and medical devices requiring extended thermal reliability without derating.
Does the LTC2122IUK#TRPBF support JESD204B subclass 1 and subclass 2 simultaneously?
No - the LTC2122IUK#TRPBF supports either JESD204B subclass 1 (using SYSREF for deterministic latency) or subclass 2 (using SYNC~ for latency initialization), but not both concurrently. Configuration is fixed at power-up via SPI register settings and cannot be dynamically switched during operation.
Can the LTC2122IUK#TRPBF operate with a single JESD204B lane at 6.0Gbps for both ADC channels?
Yes - the LTC2122IUK#TRPBF supports single-lane operation at up to 6.0Gbps, multiplexing both Channel A and Channel B data onto one CML output pair (CMLOUT_A0+/–). This reduces FPGA pin count and simplifies PCB routing compared to dual-lane implementations.
What is the purpose of the SENSE pin on the LTC2122IUK#TRPBF?
The SENSE pin on the LTC2122IUK#TRPBF selects the reference mode: tied to VDD enables the internal 1.25V reference and ±0.75V input range; applying 1.2V–1.3V externally sets the input range to ±0.6×VSENSE. This flexibility allows optimization for different signal chain gain structures without external reference ICs.
How does the clock divide-by-two feature affect sampling timing in the LTC2122IUK#TRPBF?
When enabled, the LTC2122IUK#TRPBF samples on the rising edge of DEVCLK every two cycles, effectively halving the required clock frequency while maintaining full 170Msps sampling rate. This reduces clock distribution jitter impact and eases sourcing of ultra-low-phase-noise oscillators in high-SNR systems.
LTC2122IUK#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 170M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- JESD204B
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 48-QFN (7x7)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2122IUK#TRPBF FAQ
1.How can I place an order for LTC2122IUK#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2122IUK#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2122IUK#TRPBF reliable?
The price and inventory of LTC2122IUK#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2122IUK#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2122IUK#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2122IUK#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2122IUK#TRPBF?
LTC2122IUK#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2122IUK#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2122IUK#TRPBF?
For technical support, including LTC2122IUK#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2122IUK#TRPBF requirements.
6.How does Aetrix verify that LTC2122IUK#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2122IUK#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2122IUK#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2122IUK#TRPBF?
All LTC2122IUK#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2122IUK#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2122IUK#TRPBF part is unused and in its original packaging.
Return procedure for LTC2122IUK#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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