Analog Devices Inc. LTC2140CUP-12#PBF

Overview

LTC2140CUP-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 25Msps dual-channel simultaneous-sampling analog-to-digital converter optimized for low-power, high-dynamic-range signal acquisition. It delivers 70.5dB SNR, 89dB SFDR, and 0.3LSB_RMS transition noise at 25Msps, with full-power bandwidth of 750MHz and single 1.8V supply operation. It serves in portable medical imaging and multi-channel data acquisition systems requiring precise time-aligned sampling.

For engineers reviewing the LTC2140CUP-12#PBF datasheet, LTC2140CUP-12#PBF pinout, LTC2140CUP-12#PBF application, or LTC2140CUP-12#PBF equivalent, key selection criteria include its 25Msps sample rate, 70.5dB SNR at 70MHz input, differential encode jitter of 0.10ps_RMS, CMOS/DDR CMOS/DDR LVDS output flexibility, and 0°C to 70°C commercial temperature grade in 64-pin QFN.

Technical Context

The LTC2140CUP-12#PBF implements two independent 12-bit ADC cores sharing a common sample-and-hold with 750MHz full-power bandwidth and ultralow 0.10ps_RMS jitter in differential encode mode. Its architecture supports simultaneous sampling across both channels with ±0.3LSB typical INL and no missing codes over temperature.

Digital interface options include full-rate CMOS, DDR CMOS, or DDR LVDS outputs, with separate OVDD supply enabling 1.2V–1.8V CMOS swing control. Configuration is managed via SPI port (CS/SCK/SDI/SDO) or parallel programming mode selected by PAR/SER pin.

Key Specifications

Pinout & Package

64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND), requiring soldering to PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit ADC applications.

Compared with AD9233BCPZ-25 and LTC2141CUP-12#PBF, the LTC2140CUP-12#PBF uniquely balances ultra-low power (48.4mW), guaranteed simultaneous sampling, and 70.5dB SNR in a single 64-pin QFN - making it optimal for space-constrained, battery-operated dual-channel acquisition where timing coherence and efficiency are co-prioritized.

Availability

LTC2140CUP-12#PBF is available at Aetrix Electronics and suitable for portable medical imaging, nondestructive testing, multi-channel data acquisition, and software defined radios requiring stable component supply across production lifecycles.

Supply support for LTC2140CUP-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its high-performance precision analog portfolio, emphasizing signal chain integrity, low-noise design, and robust industrial-grade reliability.

The LTC2140CUP-12#PBF belongs to the LTC214x family of dual-channel, low-power, high-SFDR ADCs engineered for communications infrastructure, portable instrumentation, and demanding mixed-signal systems where timing coherence and dynamic range are critical.

FAQ

What is the maximum input frequency supported by the LTC2140CUP-12#PBF before aliasing becomes significant?

The LTC2140CUP-12#PBF has a 750MHz full-power bandwidth and is specified for undersampling applications. With a 25Msps sampling rate, the Nyquist zone extends to 12.5MHz, but due to its 750MHz analog bandwidth, it can accurately digitize IF signals up to ~375MHz (half-bandwidth) with minimal amplitude roll-off - provided anti-alias filtering is applied outside the band of interest. The LTC2140CUP-12#PBF's 0.10ps_RMS jitter ensures phase integrity even at high IF frequencies.

Does the LTC2140CUP-12#PBF support external voltage reference operation?

Yes, the LTC2140CUP-12#PBF supports external reference mode via the SENSE pin (Pin 63), which accepts 0.625V to 1.300V. When an external reference is applied, the internal 1.25V reference is disabled, and the full-scale input range scales linearly with the SENSE voltage. This enables precise gain calibration and compatibility with external low-drift references - a capability confirmed in the "Analog Input" section of the datasheet for LTC2140-12.

How does the power consumption of the LTC2140CUP-12#PBF compare between CMOS and LVDS output modes?

In CMOS output mode at 25Msps, the LTC2140CUP-12#PBF dissipates 48.4mW total (24mW per channel). In LVDS mode, power rises significantly: 104mW total in 1.75mA mode and 155mW in 3.5mA mode. This increase stems from LVDS's constant-current drivers. The LTC2140CUP-12#PBF's separate OVDD supply allows designers to choose CMOS for ultra-low power or LVDS for noise immunity and longer trace routing - a trade-off explicitly documented in the "Power Requirements" table.

Can the LTC2140CUP-12#PBF be configured for single-ended analog input operation?

No - the LTC2140CUP-12#PBF requires differential analog inputs (AIN1+/AIN1–, AIN2+/AIN2–) and does not support true single-ended analog input. However, it supports single-ended encode clocking (by tying ENC– to GND), and the analog inputs can be driven pseudo-differentially using a resistor network referenced to VCM1/VCM2. The datasheet specifies differential input only, with common-mode rejection ratio (CMRR) of 80dB confirming its differential-input architecture.

What is the pipeline latency of the LTC2140CUP-12#PBF in double data rate CMOS mode?

The LTC2140CUP-12#PBF has a fixed pipeline latency of 6.5 cycles in double data rate (DDR) CMOS mode, as specified in the "Timing Characteristics" table under "Pipeline Latency". This value is independent of sample rate and applies across all operating conditions. For deterministic real-time processing - such as in FPGA-based digital downconverters - this latency must be accounted for in buffer sizing and timing closure; the LTC2140CUP-12#PBF's consistent 6.5-cycle delay simplifies system-level synchronization.