Analog Devices Inc. LTC2140CUP-14#TRPBF
- Part No.:
- LTC2140CUP-14#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2140CUP-14#TRPBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 64QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2140CUP-14#TRPBF from Analog Devices (formerly Linear Technology) is a 14-bit, 25Msps dual-channel simultaneous-sampling analog-to-digital converter optimized for low-power, high-dynamic-range signal acquisition in portable and battery-sensitive systems. It delivers 72.7dB SNR, 90dB SFDR, ±1LSB INL, single 1.8V supply operation, and supports CMOS/DDR CMOS/DDR LVDS digital outputs - enabling direct interface with FPGAs in portable medical imaging and multi-channel data acquisition.
For engineers reviewing the LTC2140CUP-14#TRPBF datasheet, LTC2140CUP-14#TRPBF pinout, LTC2140CUP-14#TRPBF application, or LTC2140CUP-14#TRPBF equivalent, key selection criteria include its 25Msps sampling rate, 750MHz full-power bandwidth, 50mW total power dissipation, differential encode input support, and 64-pin QFN package with exposed thermal pad.
Technical Context
The LTC2140CUP-14#TRPBF implements two independent 14-bit ADC cores sharing a common sample-and-hold with 0.10psRMS jitter in differential encode mode. Its architecture includes on-chip reference generation (1.25V VREF, VDD/2 VCM), programmable input range (1VP-P to 2VP-P via SENSE pin), and optional clock duty cycle stabilizer - all configurable via SPI or parallel control logic.
Digital output flexibility spans full-rate CMOS, DDR CMOS, and DDR LVDS modes, with separate OVDD supply (1.1V–1.9V) enabling voltage-level translation. Power management includes Nap (10mW) and Sleep (1mW) modes, while pipeline latency is fixed at 6.5 cycles in DDR output configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement. |
| Sampling Rate | 25Msps - defines maximum real-time bandwidth for baseband or undersampled IF digitization up to ~12.5MHz Nyquist. |
| SNR / SFDR | 72.7dB SNR and 90dB SFDR at 70MHz input - enables high-fidelity capture of narrowband signals in noisy RF environments. |
| Total Power | 50mW at 25Msps with CMOS outputs - supports thermally constrained portable designs without active cooling. |
| Analog Supply | Single 1.8V (1.7V–1.9V) VDD - simplifies power delivery and reduces BOM count versus dual-supply ADCs. |
| Input Bandwidth | 750MHz full-power bandwidth - preserves amplitude accuracy for fast transients and wideband signals up to UHF. |
| INL / DNL | ±1LSB integral nonlinearity and ±0.3LSB differential nonlinearity - ensures accurate amplitude linearity for calibration-critical applications. |
Pinout & Package
64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND), requiring soldering to PCB ground plane for thermal and electrical integrity. Package meets RoHS and JEDEC moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (1,16,17,64) | Analog power supply | 1.7V–1.9V supply for ADC core and reference; requires local 0.1μF ceramic bypass per group. |
| AIN1+/AIN1– (4,5) | Channel 1 differential analog input | Accepts 1VP-P to 2VP-P differential signal; biased by VCM1 (Pin 2) at VDD/2. |
| ENC+/ENC– (18,19) | Differential encode clock input | Rising edge on ENC+ initiates conversion; ENC– tied to GND enables single-ended mode. |
| PAR/SER (11) | Programming mode select | Ground = serial SPI interface (CS/SCK/SDI/SDO); VDD = parallel logic control of key functions. |
| D1_0–D1_13 / D2_0–D2_13 (25–32, 38–58, 48–49, 50–57) | Dual-channel data outputs | Configurable as CMOS (1.2V–1.8V swing) or DDR LVDS (3.5mA/1.75mA); pin mapping varies by output mode. |
| OVDD (42) | Digital output supply | Independent 1.1V–1.9V supply sets output voltage level and drives termination for LVDS mode. |
| SENSE (63) | Reference and input range select | Connect to VDD → ±1V range; connect to GND → ±0.5V range; external 0.625V–1.3V reference also supported. |
| VREF (62) | Internal reference output | 1.25V ±25ppm/°C buffered reference; requires 2.2μF ceramic bypass for stability. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous sampling dual ADC | Eliminates channel-to-channel skew for coherent multi-sensor acquisition in ultrasound or phased-array systems. |
| 750MHz full-power bandwidth | Preserves signal fidelity for fast pulse capture in NDT and time-of-flight measurements without external amplification. |
| Optional clock duty cycle stabilizer | Enables robust operation with asymmetric clocks (e.g., from PLLs or crystal oscillators), maintaining AC performance at full 25Msps rate. |
| Programmable input range (1–2VP-P) | Allows dynamic scaling to match sensor output levels - reducing need for external gain stages and preserving SNR. |
| Nap and Sleep power modes | Reduces system standby power to 10mW (Nap) or 1mW (Sleep), extending battery life in portable diagnostic equipment. |
| Serial SPI + parallel programming | Supports both firmware-driven configuration (SPI) and hardware-pin-controlled setup - simplifying integration in resource-constrained controllers. |
Applications
| Portable Medical Imaging | Multi-Channel Data Acquisition |
|---|---|
Use Scenario: Ultrasound beamforming subsystem digitizing echo return signals from multiple transducer elements. IC Role / Device Role / Timing Role: Dual-channel simultaneous ADC capturing time-aligned I/Q data streams from adjacent channels for coherent summation. Use Value: 72.7dB SNR and 750MHz bandwidth preserve weak echo amplitudes and transient detail; 50mW power enables handheld probe integration. | Use Scenario: Industrial condition monitoring system acquiring vibration, temperature, and acoustic emission data across 8+ sensors. IC Role / Device Role / Timing Role: Paired LTC2140CUP-14#TRPBF units provide four synchronized 14-bit channels with matched gain/offset for phase-coherent analysis. Use Value: ±1LSB INL and ±0.3LSB DNL ensure accurate amplitude correlation between channels; Nap mode reduces idle power during sensor polling intervals. |
| Nondestructive Testing (NDT) | Software Defined Radios (SDR) |
Use Scenario: Portable eddy-current or ultrasonic flaw detector analyzing material integrity using pulsed excitation and echo timing. IC Role / Device Role / Timing Role: High-bandwidth ADC capturing fast-rising return pulses with sub-nanosecond jitter for precise time-of-flight calculation. Use Value: 0.10psRMS jitter and 750MHz bandwidth resolve microsecond-scale delays; 25Msps rate balances resolution and memory depth in battery-powered field units. | Use Scenario: Low-SWaP cognitive radio front-end digitizing IF signals in the 10–70MHz range for spectrum sensing and adaptive modulation. IC Role / Device Role / Timing Role: Dual ADC channel processing I and Q paths simultaneously to maintain phase coherence for complex baseband reconstruction. Use Value: 90dB SFDR suppresses harmonics and intermodulation products from strong interferers; DDR LVDS outputs reduce EMI in dense RF modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS52J90IRGCT | 16-bit, 80Msps, JESD204B output, 1.8V/3.3V dual supply, 545mW typical power | Targets high-throughput base station receivers; requires FPGA with JESD204B IP and more complex power sequencing | Select when higher resolution and speed justify increased power and interface complexity. |
| AD9257BSTZ-25 | 14-bit, 25Msps, single-channel, parallel CMOS output, 1.8V supply, 45mW power | Lacks simultaneous dual-channel capability; no internal reference or SENSE-programmable range | Choose for cost-sensitive single-channel systems where channel matching is not required. |
Compared with ADS52J90IRGCT and AD9257BSTZ-25, the LTC2140CUP-14#TRPBF uniquely combines true dual-channel simultaneity, ultra-low 50mW power, integrated reference, and flexible 1–2VP-P input scaling - making it optimal for portable, battery-operated instrumentation where size, thermal envelope, and analog simplicity are critical.
Availability
LTC2140CUP-14#TRPBF is available at Aetrix Electronics and suitable for portable medical imaging, nondestructive testing, multi-channel data acquisition, and software-defined radio applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production lots.
Supply support for LTC2140CUP-14#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2140CUP-14#TRPBF belongs to ADI's legacy Linear Technology high-speed precision ADC family, engineered specifically for low-power, wide-dynamic-range digitization in portable and thermally constrained instrumentation systems.
FAQ
What is the maximum sampling rate of the LTC2140CUP-14#TRPBF?
The LTC2140CUP-14#TRPBF is rated for a maximum sampling rate of 25Msps, as specified in its ordering part number suffix "-25" and confirmed in the Dynamic Accuracy table. This rate applies across all supported output modes (CMOS, DDR CMOS, DDR LVDS) and temperature ranges (0°C to 70°C for the 'C' grade). At 25Msps, the device achieves 72.7dB SNR and 90dB SFDR with a 70MHz input signal.
Does the LTC2140CUP-14#TRPBF support differential analog inputs?
Yes, the LTC2140CUP-14#TRPBF fully supports differential analog inputs on both channels: AIN1+ and AIN1– (Pins 4 and 5) for Channel 1, and AIN2+ and AIN2– (Pins 12 and 13) for Channel 2. The device specifies ±1LSB INL and 72.7dB SNR under differential drive conditions, and common-mode rejection is 80dB. VCM1 and VCM2 pins (Pins 2 and 15) provide nominally VDD/2 bias for proper common-mode establishment.
How is the input voltage range configured on the LTC2140CUP-14#TRPBF?
The LTC2140CUP-14#TRPBF uses the SENSE pin (Pin 63) to configure input range: connecting SENSE to VDD selects a ±1V (2VP-P) range, while connecting it to GND selects a ±0.5V (1VP-P) range. An external reference between 0.625V and 1.3V may also be applied to SENSE for custom scaling. This configuration directly affects full-scale code mapping and is independent of the internal 1.25V VREF output (Pin 62).
What digital output interfaces does the LTC2140CUP-14#TRPBF support?
The LTC2140CUP-14#TRPBF supports three digital output interface types: full-rate CMOS, double-data-rate (DDR) CMOS, and DDR LVDS. Output mode is selected via SCK in parallel programming mode (PAR/SER = VDD) or SPI register write in serial mode. OVDD (Pin 42) supplies the output drivers and must be set to 1.2V, 1.5V, or 1.8V for CMOS modes, or 1.7V–1.9V for LVDS mode.
Is the LTC2140CUP-14#TRPBF pin-compatible with other members of the LTC214x-14 family?
Yes, the LTC2140CUP-14#TRPBF shares identical pinout, package (64-pin 9mm × 9mm QFN), and footprint with LTC2141CUP-14#TRPBF and LTC2142CUP-14#TRPBF. All three devices differ only in maximum sampling rate (25Msps, 40Msps, 65Msps) and corresponding power consumption, allowing drop-in replacement in designs where speed requirements change - provided timing margins and thermal design accommodate the higher-power variants.
LTC2140CUP-14#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 25M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2140CUP-14#TRPBF FAQ
1.How can I place an order for LTC2140CUP-14#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2140CUP-14#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2140CUP-14#TRPBF reliable?
The price and inventory of LTC2140CUP-14#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2140CUP-14#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2140CUP-14#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2140CUP-14#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2140CUP-14#TRPBF?
LTC2140CUP-14#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2140CUP-14#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2140CUP-14#TRPBF?
For technical support, including LTC2140CUP-14#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2140CUP-14#TRPBF requirements.
6.How does Aetrix verify that LTC2140CUP-14#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2140CUP-14#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2140CUP-14#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2140CUP-14#TRPBF?
All LTC2140CUP-14#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2140CUP-14#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2140CUP-14#TRPBF part is unused and in its original packaging.
Return procedure for LTC2140CUP-14#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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